Lines Matching refs:Addr
42 merge_address_windows(Addr, Output) :-
44 findall(range(Base, High), (rootbridge_address_window(Addr, mem(B, H)),
55 get_address_window(Addr, Min, Max) :-
56 findall(Low, rootbridge_address_window(Addr, mem(Low, _)), LowList),
57 findall(High, rootbridge_address_window(Addr, mem(_, High)), HighList),
78 findall(root(Addr,Child,mem(LP,HP), Ranges),
79 ( rootbridge(Addr,Child, _),
80 merge_address_windows(Addr, Ranges),
81 get_address_window(Addr, L, H),
179 should_shift_bridge(Addr, Sec, Root, Granularity, OrigP) :-
190 (Addr == RootAddr ->
364 %add_root_to_decoding_net(Addr, MinBus, Base, High, Ranges, Prefetchable) :-
367 % addr(Bus, Dev, Fun) = Addr,
400 add_root_to_decoding_net(Addr, MinBus, Pref, Base, High) :-
401 addr(Bus, Dev, Fun) = Addr,
411 root(Addr,childbus(MinBus,MaxBus),mem(LMem,HMem), Ranges) = Root,
419 constrain_bus(Granularity, Type, prefetchable, Addr,MinBus,MaxBus,LMem,HMem,BusElementListP, Ranges),
423 devicetree(BusElementListP,buselement(bridge,Addr,secondary(MinBus),RBaseP,RHighP,RSizeP, Type, prefetchable, pcie, 0),TP),
426 constrain_bus(Granularity, Type, nonprefetchable, Addr,MinBus,MaxBus,LMem,HMem2,BusElementListNP, Ranges),
430 devicetree(BusElementListNP,buselement(bridge,Addr,secondary(MinBus),RBaseNP,RHighNP,RSizeNP, Type, nonprefetchable, pcie, 0),TNP),
436 subtract(PPlan, [buselement(bridge,Addr, _, _, _,_,_,prefetchable,_,_)],PPlan2),
437 devicetree(PPlan2, buselement(bridge,Addr,secondary(MinBus), RBaseP, RHighP, RSizeP, Type, prefetchable, _, _), TP2),
438 add_root_to_decoding_net(Addr, MinBus, prefetchable, RBaseP, RHighP),
442 subtract(NPPlan, [buselement(bridge,Addr, _, _, _,_,_,nonprefetchable,_,_)],NPPlan2),
443 devicetree(NPPlan2, buselement(bridge,Addr,secondary(MinBus),RBaseNP,RHighNP,RSizeNP, Type, prefetchable, _, _), TNP2),
444 add_root_to_decoding_net(Addr, MinBus, nonprefetchable, RBaseNP, RHighNP),
612 ( buselement(device,Addr,BAR,Base,High,Size,_,_,_,_) = H ->
613 assert(currentbar(Addr,BAR,Base,High,Size));
621 ( buselement(device,Addr,BAR,_,_,_,_,_,_,_) = H ->
622 ( currentbar(Addr,BAR,_,_,_) ->
623 retract(currentbar(Addr,BAR,_,_,_));
695 buselement(bridge, Addr,_,Base,High,_, _, Prefetch,_,_) = Node ->
697 (not Addr == addr(-1,-1,-1) ->
795 Addr = addr(0, 0, 0),
796 rootbridge(Addr, childbus(MinBus, MaxBus), _),
797 merge_address_windows(Addr, Ranges),
798 get_address_window(Addr, L, H),
810 Root = root(Addr, childbus(MinBus, MaxBus), mem(LP, HP), Ranges),
813 constrain_bus(Granularity, mem, prefetchable, Addr,MinBus,MaxBus,LP,HP,BusElementListP, Ranges),
818 devicetree(BusElementListP,buselement(bridge,Addr,secondary(MinBus),RBaseP,RHighP,RSizeP,mem, prefetchable, _, _),Tree),