usr/arrakismon/guest.c

112 	guest_msr_area[i].val = 0x0;
363     uint8_t val = *(uint8_t *)(g->msrpm_va + byte_offset);
365     val = (val & ~(0x3 << bit_offset)) | (access_mode << bit_offset);
367     *(uint8_t *)(g->msrpm_va + byte_offset) = val;
369     //printf("MSR: msr %x, byte_offset %lx, bit_offset %x, val %x\n", msr, byte_offset, bit_offset, val);
1369 // control if val is 1 or 0, respectively.
1370 static inline void vmx_intercept_desc_table_wrf(struct guest *g, int val)
1372     assert(val == 0 || val == 1);
1376     if (val) {
1829 set_reg_val_by_reg_num (struct guest *g, uint8_t regnum, uint64_t val) {
1832         guest_set_rax(g, val);
1835         guest_set_rcx(g, val);
1838         guest_set_rdx(g, val);
1841         guest_set_rbx(g, val);
1844         guest_set_rsp(g, val);
1847         guest_set_rbp(g, val);
1850         guest_set_rsi(g, val);
1853         guest_set_rdi(g, val);
1882     uint64_t val;
1896             val = amd_vmcb_cr0_rd_raw(&g->vmcb);
1898 	    err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_CR0, &val);
1907         val = get_reg_val_by_reg_num(g, mod.u.rm);
1915             guest_set_rax(g, val);
1918             guest_set_rcx(g, val);
1921             guest_set_rdx(g, val);
1924             guest_set_rbx(g, val);
1935             amd_vmcb_cr0_wr_raw(&g->vmcb, val);
1937 	    err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_CR0, val);
2066 static inline void vmx_vmcs_rflags_cf_wrf(struct guest *g, int val) {
2067     assert(val == 0 || val == 1);
2070     if (val) {
2585     uint32_t val;
2617     // fetch the source val if neccessary
2621             val = guest_get_al(g);
2624             val = guest_get_ax(g);
2627             val = guest_get_eax(g);
2656                 r = lpc_handle_pio_write(g->lpc, port, size, val);
2659                 r = lpc_handle_pio_read(g->lpc, port, size, &val);
2669                 val = ~0;
2726                                               size, val);
2730                                              size, &val);
2748             r = pci_handle_pio_write(g->pci, port, size, val);
2750             r = pci_handle_pio_read(g->pci, port, size, &val);
2759                 val = 0xffffffff;
2768             guest_set_al(g, val);
2771             guest_set_ax(g, val);
2774             guest_set_eax(g, val);
2803     uint64_t val;
2808         val = ((uint64_t)guest_get_edx(g) << 32) | guest_get_eax(g);
2814             amd_vmcb_sysenter_cs_wr(&g->vmcb, val);
2816 	    err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_SYSENTER_CS, val);
2821             amd_vmcb_sysenter_esp_wr(&g->vmcb, val);
2823 	    err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_SYSENTER_ESP, val);
2828             amd_vmcb_sysenter_eip_wr(&g->vmcb, val);
2830 	    err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_SYSENTER_EIP, val);
2835             amd_vmcb_efer_wr_raw(&g->vmcb, val);
2837 	    err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_EFER_F, val);
2842             amd_vmcb_fs_base_wr(&g->vmcb, val);
2844 	    err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_FS_BASE, val);
2849             amd_vmcb_gs_base_wr(&g->vmcb, val);
2851 	    err += invoke_dispatcher_vmwrite(g->dcb_cap, VMX_GUEST_GS_BASE, val);
2856             amd_vmcb_kernel_gs_base_wr(&g->vmcb, val);
2859             amd_vmcb_star_wr(&g->vmcb, val);
2862             amd_vmcb_lstar_wr(&g->vmcb, val);
2865             amd_vmcb_cstar_wr(&g->vmcb, val);
2868             amd_vmcb_sfmask_wr(&g->vmcb, val);
2880 	    guest_msr_area[msr_index].val = val;
2889             val = amd_vmcb_sysenter_cs_rd(&g->vmcb);
2891 	    err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_SYSENTER_CS, &val);
2896             val = amd_vmcb_sysenter_esp_rd(&g->vmcb);
2898 	    err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_SYSENTER_ESP, &val);
2903             val = amd_vmcb_sysenter_eip_rd(&g->vmcb);
2905 	    err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_SYSENTER_EIP, &val);
2910             val = amd_vmcb_efer_rd_raw(&g->vmcb);
2912 	    err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_EFER_F, &val);
2917             val = amd_vmcb_fs_base_rd(&g->vmcb);
2919 	    err += invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_FS_BASE, &val);
2924             val = amd_vmcb_gs_base_rd(&g->vmcb);
2926 	    err = invoke_dispatcher_vmread(g->dcb_cap, VMX_GUEST_GS_BASE, &val);
2931             val = amd_vmcb_kernel_gs_base_rd(&g->vmcb);
2934             val = amd_vmcb_star_rd(&g->vmcb);
2937             val = amd_vmcb_lstar_rd(&g->vmcb);
2940             val = amd_vmcb_cstar_rd(&g->vmcb);
2943             val = amd_vmcb_sfmask_rd(&g->vmcb);
2955 	    val = guest_msr_area[msr_index].val;
2961         guest_set_eax(g, val);
2962         guest_set_edx(g, val >> 32);
3193 decode_mov_dest_val (struct guest *g, uint8_t *code, uint64_t val)
3207     set_reg_val_by_reg_num(g, modrm.u.regop, val);
3248         uint64_t val;
3254             val = decode_mov_src_val(g, code);
3255             r = apic_handle_mmio_write(g->apic, fault_addr, size, val);
3258             r = apic_handle_mmio_read(g->apic, fault_addr, size, &val);
3260             decode_mov_dest_val(g, code, val);