arch/omap4/clock.c

112 static void configure_mpu_dpll(dpll_param *dpll_param_p)
122 	sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m);
123 	sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n);
124 	sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2);
132 static void configure_iva_dpll(dpll_param *dpll_param_p)
145 	sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m);
146 	sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n);
147 	sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4);
149 	sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5);
157 static void configure_per_dpll(const dpll_param *dpll_param_p)
166 	sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m);
167 	sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n);
168 	sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2);
170 	sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3);
172 	sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4);
174 	sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5);
176 	sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6);
178 	sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7);
186 static void configure_abe_dpll(dpll_param *dpll_param_p)
198 	sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m);
199 	sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n);
203 	sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2);
207 	sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3);
215 static void configure_usb_dpll(dpll_param *dpll_param_p)
227 	sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m);
228 	sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n);
232 	sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2);
246 	dpll_param *dpll_param_p = &core_dpll_param_ddr400mhz;
263 	sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
264 	sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
265 	sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
266 	sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
267 	sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
268 	sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
269 	sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
270 	sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
282 	dpll_param *dpll_param_p = &core_dpll_param_ddr400mhz;
302 	writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);