Lines Matching refs:base
105 void reset_phy(unsigned int base)
107 writel(readl(base + IODFT_TLGC) | (1 << 10),
108 base + IODFT_TLGC);
115 static void emif_config(unsigned int base, const struct ddr_regs *ddr_regs)
129 writel(readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xBFFFFFFF,
130 base + EMIF_LPDDR2_NVM_CONFIG);
131 writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG);
134 writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1);
135 writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW);
140 writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
141 writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL_SHDW);
146 writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1);
147 writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW);
152 writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2);
153 writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW);
158 writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3);
159 writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW);
161 writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG);
172 writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
174 reg_value = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
177 writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
179 reg_value = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
184 writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
185 writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
186 writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
187 writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
193 writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
194 writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
195 writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
196 writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
200 writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
201 writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
202 writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
203 writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
206 writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG);
207 writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1);
214 writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL);
215 writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW);
218 writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG);
219 writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
221 base + EMIF_LPDDR2_MODE_REG_CFG);
222 writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);