Lines Matching refs:channel
29 xeon_phi_dma_chan_t channel; ///< Mackerel address
38 return xeon_phi_dma_chan_dcar_irq_status_rdf(&chan->channel);
44 * \param chan the dma channel to change the interrupts
54 xeon_phi_dma_chan_dcar_msix_irq_wrf(&chan->channel, mask_val);
56 xeon_phi_dma_chan_dcar_apic_irq_wrf(&chan->channel, mask_val);
59 return xeon_phi_dma_chan_dcar_rd(&chan->channel);
65 * \param chan Xeon Phi DMA channel
74 * \brief sets the error mask of a Xeon Phi DMA channel
76 * \param chan Xeon Phi DMA channel
82 xeon_phi_dma_chan_dcherrmsk_wr(&chan->channel, mask);
86 * \brief reads the tail pointer register of the Xeon Phi DMA channel
88 * \param chan Xeon Phi DMA channel
94 return xeon_phi_dma_chan_dtpr_index_rdf(&chan->channel);
98 * \brief updates the tail pointer register of the channel
100 * \param chan Xeon Phi DMA channel
107 xeon_phi_dma_chan_dtpr_index_wrf(&chan->channel, tail);
111 * \brief reads the head pointer register of the Xeon Phi DMA channel
113 * \param chan Xeon Phi DMA channel
119 return xeon_phi_dma_chan_dhpr_index_rdf(&chan->channel);
123 * \brief updates the head pointer register of the channel
125 * \param chan Xeon Phi DMA channel
132 xeon_phi_dma_chan_dhpr_index_wrf(&chan->channel, head);
136 * \brief updates the DMA statistics writeback register of the channel
138 * \param chan Xeon Phi DMA channel
150 xeon_phi_dma_chan_dstatwb_lo_wr(&chan->channel, (uint32_t) dstat_wb);
151 xeon_phi_dma_chan_dstatwb_hi_wr(&chan->channel, (uint32_t) (dstat_wb >> 32));
157 * \param chan Xeon Phi DMA channel
163 lpaddr_t addr = xeon_phi_dma_chan_dstatwb_hi_rd(&chan->channel);
165 addr |= xeon_phi_dma_chan_dstatwb_lo_rd(&chan->channel);
172 * \param chan Xeon Phi DMA channel
178 return xeon_phi_dma_chan_dstat_completions_rdf(&chan->channel);
183 * with that channel
185 * \param chan Xeon Phi DMA channel
220 * if the channel is host owned we need to set the system bit
234 xeon_phi_dma_chan_drar_lo_wr(&chan->channel, drar_lo);
235 xeon_phi_dma_chan_drar_hi_wr(&chan->channel, drar_hi);
271 * \brief initializes and allocates resources for a new channel DMA channel
275 * \param id id of this channel
277 * \param ret_chan returned channel pointer
305 XPHICHAN_DEBUG("initializig channel with max_xfer=%u\n", chan->common.id,
308 xeon_phi_dma_chan_initialize(&chan->channel,
362 * \param chan Xeon Phi DMA channel
390 * \param chan Xeon Phi DMA channel
416 * \brief Resets a IOAT DMA channel
418 * \param chan IOAT DMA channel to be reset
430 * \brief restarts a IOAT DMA channel this updates the chain address register
433 * \param chan IOAT DMA channel
445 * \brief starts a IOAT DMA channel. This sets the chain address to the first
448 * \param chan IOAT DMA channel
463 XPHICHAN_DEBUG("starting channel.\n", chan->common.id);
473 * \param chan IOAT DMA channel
485 * \brief Puts the IOAT DMA channel into the suspended state
487 * \param chan IOAT DMA channel
499 * \brief enqueues a request onto the IOAT DMA channel and submits it to the
502 * \param chan IOAT DMA channel
522 * \brief polls the IOAT DMA channel for completed events
524 * \param chan IOAT DMA channel
527 * DMA_ERR_CHAN_IDLE if there was no request on the channel
539 if (xeon_phi_dma_chan_dcherr_rd(&xchan->channel)) {
570 * \brief returns the associated IOAT DMA descriptor ring of a channel
572 * \param chan IOAT DMA channel