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  • only in /barrelfish-2018-10-04/lib/dma/ioat/

Lines Matching refs:common

28     struct dma_device common;
54 dev->common.id);
61 dev->common.id);
69 IOATDEV_DEBUG("initialize Crystal Beach 3 DMA device\n", dev->common.id);
75 dev->common.id);
80 dev->common.id);
86 IOATDEV_DEBUG("Disabling XOR and PQ while DCA is enabled\n", dev->common.id);
92 IOATDEV_DEBUG("device supports XOR RAID.\n", dev->common.id);
106 IOATDEV_DEBUG("device supports PQ RAID.\n", dev->common.id);
124 dev->common.irq_type = DMA_IRQ_DISABLED;
125 dev->common.type = DMA_DEV_TYPE_IOAT;
134 dev->common.channels.count = ioat_dma_chancnt_num_rdf(&dev->device);
136 dev->common.channels.c = calloc(dev->common.channels.count,
137 sizeof(*dev->common.channels.c));
138 if (dev->common.channels.c == NULL) {
145 IOATDEV_DEBUG("channel enumeration. discovered %u channels\n", dev->common.id,
146 dev->common.channels.count);
150 for (uint8_t i = 0; i < dev->common.channels.count; ++i) {
151 struct dma_channel **chan = &dev->common.channels.c[i];
180 if (dev->common.state != DMA_DEV_ST_CHAN_ENUM) {
188 mem->paddr += (IOAT_DMA_COMPLSTATUS_SIZE * dev->common.channels.next);
190 mem->vaddr += (IOAT_DMA_COMPLSTATUS_SIZE * dev->common.channels.next++);
247 dev->common.irq_type = type;
252 dev->common.id, dev->pci_addr.bus, dev->pci_addr.device,
262 IOATDEV_DEBUG("MSI-X enabled #vecs=%d\n", dev->common.id,
271 IOATDEV_DEBUG("MSI-X routing to apic=%u\n", dev->common.id,
283 IOATDEV_DEBUG("Initializing MSI interrupts \n", dev->common.id);
287 IOATDEV_DEBUG("Initializing INTx interrupts \n", dev->common.id);
293 IOATDEV_DEBUG("Disabling interrupts \n", dev->common.id);
307 chan = (struct ioat_dma_channel *)dev->common.channels.c[0];
375 struct dma_device *dma_dev = &ioat_device->common;