Lines Matching refs:slot
13 static ahci_port_chdr_t get_command_header(struct ahci_port* port, uint8_t slot)
15 return (ahci_port_chdr_t) ((uint8_t*)port->clb.vaddr) + (ahci_port_chdr_size * slot);
92 for (size_t slot = 0; slot < slots; slot++) {
93 struct dev_queue_request *dqr = &reqs[slot];
96 bool slot_done = ahci_port_slot_free(&port->port, slot);
98 //printf("waiting for slot %zu.\n", slot);
126 errval_t blk_ahci_port_dma_async(struct ahci_port *port, size_t slot, uint64_t block, lpaddr_t base, size_t length, bool write)
129 assert(ahci_port_slot_free(&port->port, 1 << slot));
133 ahci_port_chdr_t header = get_command_header(port, slot);
139 ahci_port_chdr_ctba_insert(header, port->ctba_mem[slot].paddr);
144 struct command_table* ct = port->command_table[slot];
155 // Issue command in slot 0
156 ahci_port_ci_rawwr(&port->port, 1 << slot);
160 while ((ahci_port_ci_rd(&port->port) & (1<<slot)) > 0) {
173 size_t slot = 0;
175 // TODO: use only slot 0
176 assert(ahci_port_slot_free(&port->port, 1 << slot));
178 ahci_port_chdr_t header = get_command_header(port, slot);
184 ahci_port_chdr_ctba_insert(header, port->ctba_mem[slot].paddr);
190 struct command_table* ct = port->command_table[slot];
200 // Issue command in slot 0
201 ahci_port_ci_wr(&port->port, 1 << slot);
204 while ((ahci_port_ci_rd(&port->port) & (1<<slot)) > 0) {
265 // Issue command in slot 0
358 for (size_t slot = 0; slot < ncs; slot++) {
359 port_init_ctba(port, slot);