Lines Matching refs:port
13 static ahci_port_chdr_t get_command_header(struct ahci_port* port, uint8_t slot)
15 return (ahci_port_chdr_t) ((uint8_t*)port->clb.vaddr) + (ahci_port_chdr_size * slot);
35 static errval_t port_init_fb(struct ahci_port* port)
37 assert(port != NULL);
39 errval_t err = dma_mem_alloc(1024, &port->fb);
44 memset((void*)port->fb.vaddr, 0x0, 1024);
46 assert(port->fb.paddr % 4096 == 0);
47 ahci_port_fb_wr(&port->port, port->fb.paddr);
51 static errval_t port_init_clb(struct ahci_port* port)
53 assert (port != NULL);
56 errval_t err = dma_mem_alloc(ahci_port_chdr_size*32, &port->clb);
61 memset((void*)port->clb.vaddr, 0x0, ahci_port_chdr_size*32);
63 assert(port->clb.paddr % 1024 == 0);
64 ahci_port_clb_wr(&port->port, port->clb.paddr);
68 static errval_t port_init_ctba(struct ahci_port* port, size_t command_slot)
70 assert(port != NULL);
73 errval_t err = dma_mem_alloc(4096, &port->ctba_mem[command_slot]);
78 memset((void*)port->ctba_mem[command_slot].vaddr, 0x0, 4096);
79 port->command_table[command_slot] = (struct command_table*) port->ctba_mem[command_slot].vaddr;
84 static void blk_ahci_interrupt(struct ahci_port* port, struct dev_queue_request* reqs,
87 ahci_port_is_t status = ahci_port_is_rd(&port->port);
96 bool slot_done = ahci_port_slot_free(&port->port, slot);
106 ahci_port_is_dhrs_wrf(&port->port, 0x1);
114 ahci_port_is_pr(buf, 4096, &port->port);
115 BLK_DEBUG("GOT unhandled IRQ: %u\n", ahci_port_is_rd(&port->port));
118 printf("[BLK] unhandled irq: %u", ahci_port_is_rd(&port->port));
126 errval_t blk_ahci_port_dma_async(struct ahci_port *port, size_t slot, uint64_t block, lpaddr_t base, size_t length, bool write)
129 assert(ahci_port_slot_free(&port->port, 1 << slot));
133 ahci_port_chdr_t header = get_command_header(port, slot);
139 ahci_port_chdr_ctba_insert(header, port->ctba_mem[slot].paddr);
144 struct command_table* ct = port->command_table[slot];
150 while (!ahci_port_is_ready(&port->port)) {
156 ahci_port_ci_rawwr(&port->port, 1 << slot);
160 while ((ahci_port_ci_rd(&port->port) & (1<<slot)) > 0) {
170 errval_t blk_ahci_port_dma(struct ahci_port *port, uint64_t block, struct dma_mem *buffer, bool write)
176 assert(ahci_port_slot_free(&port->port, 1 << slot));
178 ahci_port_chdr_t header = get_command_header(port, slot);
184 ahci_port_chdr_ctba_insert(header, port->ctba_mem[slot].paddr);
190 struct command_table* ct = port->command_table[slot];
196 while (!ahci_port_is_ready(&port->port)) {
201 ahci_port_ci_wr(&port->port, 1 << slot);
204 while ((ahci_port_ci_rd(&port->port) & (1<<slot)) > 0) {
211 ahci_port_is_dhrs_wrf(&port->port, 0x1);
213 if (ahci_port_is_rd(&port->port) != 0x0) {
216 ahci_port_is_pr(buf, 4096, &port->port);
217 BLK_DEBUG("GOT unhandled IRQ: %u\n", ahci_port_is_rd(&port->port));
226 static errval_t port_identify(struct ahci_port *port)
230 assert(ahci_port_slot_free(&port->port, 1));
232 err = dma_mem_alloc(512, &port->identify_mem);
236 memset((void*)port->identify_mem.vaddr, 0, 512);
239 ahci_port_chdr_t header = get_command_header(port, 0);
245 ahci_port_chdr_ctba_insert(header, port->ctba_mem[0].paddr);
247 struct command_table* ct = port->command_table[0];
257 ct->prdt[0] = region_descriptor_new(port->identify_mem.paddr, 511, false);
259 while (!ahci_port_is_ready(&port->port)) {}
262 ahci_port_cmd_t cmd = ahci_port_cmd_rd(&port->port);
266 ahci_port_ci_wr(&port->port, 0x1);
269 while ((ahci_port_ci_rd(&port->port) & 0x1) > 0) {
275 ahci_port_is_pss_wrf(&port->port, 0x1);
278 if (ahci_port_is_rd(&port->port) != 0x0) {
281 ahci_port_is_pr(buf, 4096, &port->port);
282 BLK_DEBUG("GOT unhandled IRQ: %u\n", ahci_port_is_rd(&port->port));
286 assert(ahci_port_is_rd(&port->port) == 0x0);
289 ata_identify_initialize(&port->identify, (mackerel_addr_t)port->identify_mem.vaddr);
292 ahci_port_print_identification(&port->identify);
308 // map value will aid software in determining how many ports are available and which port
311 struct ahci_port *port = &ad->ports[i];
315 ahci_port_initialize(&port->port, (mackerel_addr_t)base_address + ahci_port_offset(i));
317 BLK_DEBUG("Initializing port: %zu\n", i);
318 uint32_t probe = ahci_port_probe(&port->port);
327 BLK_DEBUG("Port %zu unkown signature: %d\n", i, ahci_port_sig_rd(&port->port));
332 // implemented port���s PxCMD register. If PxCMD.ST, PxCMD.CR, PxCMD.FRE and
333 // PxCMD.FR are all cleared, the port is in an idle state.
334 if (!ahci_port_is_idle(&port->port)) {
336 ahci_port_stop(&port->port);
338 assert(ahci_port_is_idle(&port->port)); // if this triggers, try a port reset...
340 // For each implemented port, system software shall allocate memory for and program:
343 port_init_clb(port);
344 port_init_fb(port);
348 ahci_port_cmd_fre_wrf(&port->port, 0x1);
350 // For each implemented port, clear the PxSERR register, by writing ���1s��� to each bit location.
351 uint32_t serr = ahci_port_serr_rd(&port->port);
352 ahci_port_serr_wr(&port->port, serr);
354 // Determine which events should cause an interrupt, and set each implemented port���s PxIE
355 ahci_port_ie_wr(&port->port, 0xffffffff);
359 port_init_ctba(port, slot);
362 BLK_DEBUG("Waiting for port %zu to become ready\n", i);
363 while(!ahci_port_is_functional(&port->port)) {
366 ahci_port_start(&port->port);
368 BLK_DEBUG("Initialized port %zu\n", i);
369 err = port_identify(port);
372 port->ncs = ahci_hba_get_command_slots(&ad->controller);
373 port->interrupt = blk_ahci_interrupt;
374 port->is_initialized = true;