sim/frv/profile-fr500.c

226 frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc,
233 frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc,
279 frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc,
330 frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
398 frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc,
461 frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc,
505 frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc,
531 frvbf_model_fr500_u_clrgr (SIM_CPU *cpu, const IDESC *idesc,
557 frvbf_model_fr500_u_clrfr (SIM_CPU *cpu, const IDESC *idesc,
583 frvbf_model_fr500_u_commit (SIM_CPU *cpu, const IDESC *idesc,
618 frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
647 frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
713 frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
770 frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc,
789 frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
869 frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
930 frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc,
949 frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc,
994 frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc,
1035 frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
1070 frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
1099 frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
1144 frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
1181 frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc,
1219 frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc,
1257 frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
1295 frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
1333 frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
1371 frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc,
1409 frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
1447 frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc,
1518 frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc,
1632 frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc,
1685 frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1750 frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1808 frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc,
1843 frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc,
1887 frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc,
1964 frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc,
2029 frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
2130 frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc,
2249 frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc,
2352 frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc,
2543 frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc,
2659 frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
2743 frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc,
2886 frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc,
2896 frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
2974 frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc,
3105 frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
3143 frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc,
3181 frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3190 frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3199 frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc,