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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/

Lines Matching refs:VA

480   /* The VA field in a VA, VX or VXR form instruction.  */
481 #define VA UI + 1
484 /* The VB field in a VA, VX or VXR form instruction. */
485 #define VB VA + 1
488 /* The VC field in a VA form instruction. */
492 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
506 /* The SHB field in a VA form instruction. */
1400 /* An VA form instruction. */
1403 /* The mask for an VA form instruction. */
1933 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1934 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1935 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1936 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1937 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1938 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1939 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1940 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1941 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1942 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1943 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1944 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1945 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1946 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1947 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1948 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1949 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1950 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1951 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1954 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1955 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1956 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1957 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1958 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1959 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1960 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1961 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1962 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1963 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1964 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1965 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1966 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1967 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1968 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1969 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1970 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1971 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1972 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1973 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1974 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1975 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1976 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1977 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1978 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1979 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1984 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1985 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1986 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1987 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1988 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1989 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1990 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1991 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1992 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1993 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1994 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1995 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1996 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1997 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1998 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1999 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2000 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2001 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2002 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2003 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2004 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2005 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2006 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2007 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2008 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2009 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2010 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2011 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2012 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2013 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2014 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2015 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2016 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2017 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2018 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2019 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2020 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2021 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2022 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2023 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2024 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2025 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2026 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2027 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2028 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2029 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2030 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2031 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2032 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2033 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2034 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2040 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2041 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2042 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2044 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2045 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2046 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2047 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2048 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2049 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2050 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2057 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2058 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2059 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2060 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2061 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2062 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2063 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2064 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2065 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2066 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2067 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2068 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2069 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2070 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2072 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2073 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2074 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2075 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2076 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2077 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2078 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2079 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2080 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2087 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },