Lines Matching refs:me
105 static void deliver_tx3904tmr_tick (struct hw *me, void *data);
202 attach_tx3904tmr_regs (struct hw *me,
210 if (hw_find_property (me, "reg") == NULL)
211 hw_abort (me, "Missing \"reg\" property");
213 if (!hw_find_reg_array_property (me, "reg", 0, ®))
214 hw_abort (me, "\"reg\" property must contain one addr/size entry");
216 hw_unit_address_to_attach_address (hw_parent (me),
220 me);
221 hw_unit_size_to_attach_size (hw_parent (me),
223 &attach_size, me);
225 hw_attach_address (hw_parent (me), 0,
227 me);
229 if(hw_find_property(me, "clock") != NULL)
230 controller->clock_ticks = (unsigned_4) hw_find_integer_property(me, "clock");
232 if(hw_find_property(me, "ext") != NULL)
233 controller->ext_ticks = (unsigned_4) hw_find_integer_property(me, "ext");
240 tx3904tmr_finish (struct hw *me)
244 controller = HW_ZALLOC (me, struct tx3904tmr);
245 set_hw_data (me, controller);
246 set_hw_io_read_buffer (me, tx3904tmr_io_read_buffer);
247 set_hw_io_write_buffer (me, tx3904tmr_io_write_buffer);
248 set_hw_ports (me, tx3904tmr_ports);
249 set_hw_port_event (me, tx3904tmr_port_event);
256 attach_tx3904tmr_regs (me, controller);
277 tx3904tmr_port_event (struct hw *me,
283 struct tx3904tmr *controller = hw_data (me);
289 HW_TRACE ((me, "reset"));
304 hw_event_queue_deschedule(me, controller->event);
310 hw_abort (me, "Event on unknown port %d", my_port);
319 tx3904tmr_io_read_buffer (struct hw *me,
325 struct tx3904tmr *controller = hw_data (me);
328 HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
361 tx3904tmr_io_write_buffer (struct hw *me,
367 struct tx3904tmr *controller = hw_data (me);
370 HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
392 /* HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr)); */
404 /* HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr)); */
412 /* HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr)); */
425 /* HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr)); */
438 /* HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr)); */
450 hw_port_event(me, INT_PORT, 0);
456 /* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */
464 /* HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra)); */
472 /* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */
476 HW_TRACE ((me, "write to illegal register %d", reg_number));
482 hw_event_queue_schedule(me, 1, deliver_tx3904tmr_tick, NULL);
491 deliver_tx3904tmr_tick (struct hw *me,
494 struct tx3904tmr *controller = hw_data (me);
495 SIM_DESC sd = hw_system (me);
512 hw_event_queue_deschedule(me, controller->event);
607 hw_port_event(me, INT_PORT, 1);
626 hw_port_event(me, FF_PORT, controller->ff);
632 hw_port_event(me, INT_PORT, 1);
641 hw_port_event(me, FF_PORT, controller->ff);
647 hw_port_event(me, INT_PORT, 1);
666 hw_port_event(me, INT_PORT, 1);
682 /* HW_TRACE ((me, "counter trr %ld tisr %lx",
689 controller->event = hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);