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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/

Lines Matching defs:SH

413   /* The SH field in an X or M form instruction.  */
414 #define SH RSO + 1
417 #define EVUIMM SH
420 /* The SH field in an MD form instruction. This is split. */
421 #define SH6 SH + 1
425 /* The SH field of the tlbwe instruction, which is optional. */
560 /* SH field starting at bit position 16. */
1156 /* The SH field in an MD form instruction. This is split. */
1370 /* An M_MASK with the SH and ME fields fixed. */
1380 /* An MD_MASK with the SH field fixed. */
1472 /* An X form tlb instruction with the SH field specified. */
3075 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3076 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3078 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3079 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3081 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3083 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3084 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3085 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3087 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3088 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3414 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3415 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3495 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3496 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
4209 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4210 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4233 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4234 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4267 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4268 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4269 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4270 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4315 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4316 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },