Lines Matching refs:pi
69 static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk);
70 static int pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write, uint *val);
71 static int pciegen1_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
73 static int pciegen2_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
75 static int pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint readdr, uint val);
76 static int pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint readdr, uint *ret_val);
78 static void pcie_extendL1timer(pcicore_info_t *pi, bool extend);
79 static void pcie_clkreq_upd(pcicore_info_t *pi, uint state);
81 static void pcie_war_aspm_clkreq(pcicore_info_t *pi);
82 static void pcie_war_serdes(pcicore_info_t *pi);
83 static void pcie_war_noplldown(pcicore_info_t *pi);
84 static void pcie_war_polarity(pcicore_info_t *pi);
85 static void pcie_war_pci_setup(pcicore_info_t *pi);
86 static void pcie_power_save_upd(pcicore_info_t *pi, bool up);
88 static bool pcicore_pmecap(pcicore_info_t *pi);
140 pcicore_info_t *pi;
146 if ((pi = MALLOC(osh, sizeof(pcicore_info_t))) == NULL) {
151 bzero(pi, sizeof(pcicore_info_t));
153 pi->sih = sih;
154 pi->osh = osh;
157 pi->regs.pcieregs = (sbpcieregs_t*)regs;
158 cap_ptr = pcicore_find_pci_capability(pi->osh, PCI_CAP_PCIECAP_ID, NULL, NULL);
160 pi->pciecap_devctrl_offset = cap_ptr + PCIE_CAP_DEVCTRL_OFFSET;
161 pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
162 pi->pciecap_devctrl2_offset = cap_ptr + PCIE_CAP_DEVCTRL2_OFFSET;
163 pi->pciecap_ltr0_reg_offset = cap_ptr + PCIE_CAP_LTR0_REG_OFFSET;
164 pi->pciecap_ltr1_reg_offset = cap_ptr + PCIE_CAP_LTR1_REG_OFFSET;
165 pi->pciecap_ltr2_reg_offset = cap_ptr + PCIE_CAP_LTR2_REG_OFFSET;
167 pi->regs.pcieregs = (sbpcieregs_t*)regs;
168 cap_ptr = pcicore_find_pci_capability(pi->osh, PCI_CAP_PCIECAP_ID, NULL, NULL);
170 pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
171 pi->pciecap_devctrl_offset = cap_ptr + PCIE_CAP_DEVCTRL_OFFSET;
172 pi->pciecap_devctrl2_offset = cap_ptr + PCIE_CAP_DEVCTRL2_OFFSET;
173 pi->pciecap_ltr0_reg_offset = cap_ptr + PCIE_CAP_LTR0_REG_OFFSET;
174 pi->pciecap_ltr1_reg_offset = cap_ptr + PCIE_CAP_LTR1_REG_OFFSET;
175 pi->pciecap_ltr2_reg_offset = cap_ptr + PCIE_CAP_LTR2_REG_OFFSET;
176 pi->pcie_power_save = TRUE; /* Enable pcie_power_save by default */
178 pi->regs.pciregs = (sbpciregs_t*)regs;
180 return pi;
186 pcicore_info_t *pi = (pcicore_info_t *)pch;
189 if (pi == NULL)
191 MFREE(pi->osh, pi, sizeof(pcicore_info_t));
320 pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
322 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
328 W_REG(pi->osh, &pcieregs->u.pcie1.mdiodata, mdiodata);
333 if (R_REG(pi->osh, &(pcieregs->u.pcie1.mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
349 pcie2_mdiosetblock(pcicore_info_t *pi, uint blk)
351 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
356 W_REG(pi->osh, &pcieregs->u.pcie2.mdiocontrol, mdioctrl);
359 W_REG(pi->osh, &pcieregs->u.pcie2.mdiowrdata, mdiodata);
364 if (!(R_REG(pi->osh, &(pcieregs->u.pcie2.mdiowrdata)) & MDIODATA2_DONE)) {
380 pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write, uint *val)
382 if (PCIE_GEN1(pi->sih))
383 return (pciegen1_mdioop(pi, physmedia, regaddr, write, val));
384 else if (PCIE_GEN2(pi->sih))
385 return (pciegen2_mdioop(pi, physmedia, regaddr, write, val, 0));
391 pciegen2_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write, uint *val,
394 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
398 if (!PCIE_GEN2(pi->sih))
401 pcie2_mdiosetblock(pi, physmedia);
413 W_REG(pi->osh, (&pcieregs->u.pcie2.mdiocontrol), mdio_ctrl);
416 W_REG(pi->osh, reg32, *val | MDIODATA2_DONE);
423 if (!(R_REG(pi->osh, reg32) & MDIODATA2_DONE)) {
425 *val = (R_REG(pi->osh, reg32) & MDIODATA2_MASK);
435 pciegen1_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write, uint *val)
437 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
442 if (!PCIE_GEN1(pi->sih))
446 W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
448 if (pi->sih->buscorerev >= 10) {
450 if (!pcie_mdiosetblock(pi, physmedia))
465 W_REG(pi->osh, &pcieregs->u.pcie1.mdiodata, mdiodata);
471 if (R_REG(pi->osh, &(pcieregs->u.pcie1.mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
474 *val = (R_REG(pi->osh, &(pcieregs->u.pcie1.mdiodata)) &
478 W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), 0);
487 W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), 0);
493 pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint regaddr, uint *regval)
495 return pcie_mdioop(pi, physmedia, regaddr, FALSE, regval);
500 pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val)
502 return pcie_mdioop(pi, physmedia, regaddr, TRUE, &val);
516 pcicore_info_t *pi = (pcicore_info_t *)pch;
520 offset = pi->pciecap_devctrl_offset;
524 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
528 if (PCIE_GEN1(pi->sih) && (pi->sih->buscorerev < 18)) {
530 __FUNCTION__, pi->sih->buscorerev));
538 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
539 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
547 pcicore_info_t *pi = (pcicore_info_t *)pch;
551 offset = pi->pciecap_devctrl_offset;
555 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
561 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
562 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
570 pcicore_info_t *pi = (pcicore_info_t *)pch;
574 offset = pi->pciecap_lcreg_offset;
578 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
585 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
586 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
597 pcicore_info_t *pi = (pcicore_info_t *)pch;
601 offset = pi->pciecap_devctrl2_offset;
605 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
613 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
614 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
632 pcicore_info_t *pi = (pcicore_info_t *)pch;
636 offset = pi->pciecap_devctrl2_offset;
640 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
647 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
648 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
657 pcicore_info_t *pi = (pcicore_info_t *)pch;
661 if (PCIE_GEN1(pi->sih))
665 offset = pi->pciecap_ltr0_reg_offset;
667 offset = pi->pciecap_ltr1_reg_offset;
669 offset = pi->pciecap_ltr2_reg_offset;
681 pcie_writereg(pi->sih, pi->regs.pcieregs, PCIE_CONFIGREGS, offset, reg_val);
684 reg_val = pcie_readreg(pi->sih, pi->regs.pcieregs, PCIE_CONFIGREGS, offset);
693 pcicore_info_t *pi = (pcicore_info_t *)pch;
694 si_t *sih = pi->sih;
695 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
705 W_REG(pi->osh, &(pcieregs->ltrspacing), val);
708 retval = R_REG(pi->osh, &(pcieregs->ltrspacing));
717 pcicore_info_t *pi = (pcicore_info_t *)pch;
718 si_t *sih = pi->sih;
719 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
729 W_REG(pi->osh, &(pcieregs->ltrhysteresiscnt), val);
732 retval = R_REG(pi->osh, &(pcieregs->ltrhysteresiscnt));
739 pcie_extendL1timer(pcicore_info_t *pi, bool extend)
742 si_t *sih = pi->sih;
743 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
760 pcie_clkreq_upd(pcicore_info_t *pi, uint state)
762 si_t *sih = pi->sih;
771 pcie_clkreq((void *)pi, 1, 0);
779 } else if (pi->pcie_pr42767) {
780 pcie_clkreq((void *)pi, 1, 1);
790 pcie_clkreq((void *)pi, 1, 0);
802 pcie_war_polarity(pcicore_info_t *pi)
806 if (pi->pcie_polarity != 0)
809 w = pcie_readreg(pi->sih, pi->regs.pcieregs, PCIE_PCIEREGS, PCIE_PLP_STATUSREG);
815 pi->pcie_polarity = (SERDES_RX_CTRL_FORCE);
817 pi->pcie_polarity = (SERDES_RX_CTRL_FORCE | SERDES_RX_CTRL_POLARITY);
827 pcie_war_aspm_clkreq(pcicore_info_t *pi)
829 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
830 si_t *sih = pi->sih;
841 val16 = R_REG(pi->osh, reg16);
844 if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
846 else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB)
848 else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
851 W_REG(pi->osh, reg16, val16);
853 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(uint32));
855 w |= pi->pcie_war_aspm_ovr;
856 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(uint32), w);
860 val16 = R_REG(pi->osh, reg16);
862 if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
864 pi->pcie_pr42767 = TRUE;
868 W_REG(pi->osh, reg16, val16);
872 pcie_war_pmebits(pcicore_info_t *pi)
874 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
877 if (pi->sih->buscorerev != 18 && pi->sih->buscorerev != 19)
881 val16 = R_REG(pi->osh, reg16);
882 if (val16 != pi->pmebits) {
884 val16, pi->pmebits));
885 pi->pmebits = 0x1f30;
886 W_REG(pi->osh, reg16, pi->pmebits);
887 val16 = R_REG(pi->osh, reg16);
895 pcie_war_serdes(pcicore_info_t *pi)
899 if (pi->pcie_polarity != 0)
900 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL, pi->pcie_polarity);
902 pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
905 pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
912 BCMINITFN(pcie_misc_config_fixup)(pcicore_info_t *pi)
914 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
918 val16 = R_REG(pi->osh, reg16);
922 W_REG(pi->osh, reg16, val16);
928 pcie_war_noplldown(pcicore_info_t *pi)
930 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
933 ASSERT(pi->sih->buscorerev == 7);
936 si_corereg(pi->sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
941 W_REG(pi->osh, reg16, 0);
946 pcie_war_pci_setup(pcicore_info_t *pi)
948 si_t *sih = pi->sih;
949 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
965 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
966 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
967 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
975 pcie_war_serdes(pi);
977 pcie_war_aspm_clkreq(pi);
978 } else if (pi->sih->buscorerev == 7)
979 pcie_war_noplldown(pi);
982 if (pi->sih->buscorerev >= 6)
983 pcie_misc_config_fixup(pi);
989 pcicore_info_t *pi = (pcicore_info_t *)pch;
991 if (!PCIE_GEN1(pi->sih))
994 if (!PCIEGEN1_ASPM(pi->sih))
1001 pi->pcie_war_aspm_ovr = aspm;
1004 pcie_war_aspm_clkreq(pi);
1011 pcicore_info_t *pi = (pcicore_info_t *)pch;
1014 if (!pi)
1017 pi->pcie_power_save = enable;
1021 pcie_power_save_upd(pcicore_info_t *pi, bool up)
1023 si_t *sih = pi->sih;
1025 if (!pi->pcie_power_save)
1031 pcicore_pcieserdesreg(pi, MDIO_DEV_BLK1, BLK1_PWR_MGMT1, 1, 0x7F64);
1034 pcicore_pcieserdesreg(pi, MDIO_DEV_BLK1, BLK1_PWR_MGMT3, 1, 0x74);
1036 pcicore_pcieserdesreg(pi, MDIO_DEV_BLK1, BLK1_PWR_MGMT3, 1, 0x7C);
1040 pcicore_pcieserdesreg(pi, MDIO_DEV_BLK1, BLK1_PWR_MGMT1, 1, 0x7E65);
1043 pcicore_pcieserdesreg(pi, MDIO_DEV_BLK1, BLK1_PWR_MGMT3, 1, 0x175);
1045 pcicore_pcieserdesreg(pi, MDIO_DEV_BLK1, BLK1_PWR_MGMT3, 1, 0x17D);
1052 pcicore_info_t *pi = (pcicore_info_t *)pch;
1055 if (!pi)
1058 sih = pi->sih;
1061 pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_128B;
1063 pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_256B;
1065 pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_512B;
1067 pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_1024B;
1072 if (pi->sih->buscorerev == 18 || pi->sih->buscorerev == 19)
1073 pcie_devcontrol_mrrs(pi, PCIE_CAP_DEVCTRL_MRRS_MASK,
1074 (uint32)pi->pcie_reqsize);
1077 pcie_devcontrol_mrrs(pi, PCIE_CAP_DEVCTRL_MRRS_MASK, (uint32)pi->pcie_reqsize);
1086 pcicore_info_t *pi = (pcicore_info_t *)pch;
1088 if (!pi)
1091 if (pi->pcie_reqsize == PCIE_CAP_DEVCTRL_MRRS_128B)
1093 else if (pi->pcie_reqsize == PCIE_CAP_DEVCTRL_MRRS_256B)
1095 else if (pi->pcie_reqsize == PCIE_CAP_DEVCTRL_MRRS_512B)
1103 pcicore_info_t *pi = (pcicore_info_t *)pch;
1105 if (!pi)
1109 pi->pcie_mps = PCIE_CAP_DEVCTRL_MPS_128B;
1111 pi->pcie_mps = PCIE_CAP_DEVCTRL_MPS_256B;
1113 pi->pcie_mps = PCIE_CAP_DEVCTRL_MPS_512B;
1115 pi->pcie_mps = PCIE_CAP_DEVCTRL_MPS_1024B;
1119 pcie_devcontrol_mps(pi, PCIE_CAP_DEVCTRL_MPS_MASK, (uint32)pi->pcie_mps);
1125 pcicore_info_t *pi = (pcicore_info_t *)pch;
1127 if (!pi)
1130 if (pi->pcie_mps == PCIE_CAP_DEVCTRL_MPS_128B)
1132 else if (pi->pcie_mps == PCIE_CAP_DEVCTRL_MPS_256B)
1134 else if (pi->pcie_mps == PCIE_CAP_DEVCTRL_MPS_512B)
1136 else if (pi->pcie_mps == PCIE_CAP_DEVCTRL_MPS_1024B)
1145 pcicore_info_t *pi = (pcicore_info_t *)pch;
1146 si_t *sih = pi->sih;
1158 pcicore_info_t *pi = (pcicore_info_t *)pch;
1159 si_t *sih = pi->sih;
1160 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1179 pcicore_info_t *pi = (pcicore_info_t *)pch;
1180 si_t *sih = pi->sih;
1181 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1197 pcicore_info_t *pi = (pcicore_info_t *)pch;
1198 si_t *sih = pi->sih;
1199 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1207 data = pcie_readreg(sih, pcieregs, PCIE_CONFIGREGS, pi->pciecap_lcreg_offset);
1208 pcie_writereg(sih, pcieregs, PCIE_CONFIGREGS, pi->pciecap_lcreg_offset, data | 2);
1215 data = OSL_PCI_READ_CONFIG(pi->osh, PCIECFGREG_PML1_SUB_CTRL1, sizeof(uint32)) & 0xfffffff0;
1224 OSL_PCI_WRITE_CONFIG(pi->osh, PCIECFGREG_PML1_SUB_CTRL1, sizeof(uint32), data);
1230 pcicore_info_t *pi = (pcicore_info_t *)pch;
1231 si_t *sih = pi->sih;
1237 data = OSL_PCI_READ_CONFIG(pi->osh, PCIECFGREG_PML1_SUB_CTRL1, sizeof(uint32));
1253 pcicore_info_t *pi = (pcicore_info_t *)pch;
1254 si_t *sih = pi->sih;
1262 pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_1024B;
1271 pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
1273 pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
1277 pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_128B;
1279 pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_512B;
1281 bzero(pi->pcie_configspace, PCI_CONFIG_SPACE_SIZE);
1284 pcie_war_polarity(pi);
1286 pcie_war_serdes(pi);
1288 pcie_war_aspm_clkreq(pi);
1290 pcie_clkreq_upd(pi, state);
1292 pcie_war_pmebits(pi);
1308 pcicore_info_t *pi = (pcicore_info_t *)pch;
1310 if (!pi || !PCIE_GEN1(pi->sih))
1313 pcie_power_save_upd(pi, TRUE);
1315 if (pi->sih->boardtype == CB2_4321_BOARD || pi->sih->boardtype == CB2_4321_AG_BOARD)
1318 pcie_war_pci_setup(pi);
1321 if (pi->sih->boardvendor == VENDOR_APPLE) {
1322 if (pi->sih->boardtype == 0x8d)
1325 else if (PCIE_DRIVE_STRENGTH_OVERRIDE(pi->sih))
1334 pcicore_info_t *pi = (pcicore_info_t *)pch;
1336 if (!pi)
1339 if (PCIE_GEN2(pi->sih)) {
1340 pcie_devcontrol_mrrs(pi, PCIE_CAP_DEVCTRL_MRRS_MASK, pi->pcie_reqsize);
1344 pcie_power_save_upd(pi, TRUE);
1347 pcie_extendL1timer(pi, TRUE);
1349 pcie_clkreq_upd(pi, state);
1351 if (pi->sih->buscorerev == 18 ||
1352 (pi->sih->buscorerev == 19 && !PCIE_MRRS_OVERRIDE(sih)))
1353 pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_128B;
1355 pcie_devcontrol_mrrs(pi, PCIE_CAP_DEVCTRL_MRRS_MASK, pi->pcie_reqsize);
1362 pcicore_info_t *pi = (pcicore_info_t *)pch;
1365 if (!pi || !PCIE_GEN1(pi->sih))
1368 pcie_power_save_upd(pi, FALSE);
1371 if (!PCIEGEN1_ASPM(pi->sih))
1375 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(uint32));
1377 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(uint32), w);
1380 pi->pcie_pr42767 = FALSE;
1386 pcicore_info_t *pi = (pcicore_info_t *)pch;
1388 if (!pi || !PCIE_GEN1(pi->sih))
1391 pcie_clkreq_upd(pi, state);
1394 pcie_extendL1timer(pi, FALSE);
1396 pcie_power_save_upd(pi, FALSE);
1422 pcicore_pmecap(pcicore_info_t *pi)
1426 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1429 if (!pi->pmecap_offset) {
1430 cap_ptr = pcicore_find_pci_capability(pi->osh, PCI_CAP_POWERMGMTCAP_ID, NULL, NULL);
1434 pi->pmecap_offset = cap_ptr;
1437 pi->pmebits = R_REG(pi->osh, reg16);
1439 pmecap = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset, sizeof(uint32));
1442 pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
1445 return (pi->pmecap);
1452 pcicore_info_t *pi = (pcicore_info_t *)pch;
1456 if (!pcicore_pmecap(pi))
1459 pcie_war_pmebits(pi);
1461 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
1463 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32), w);
1470 pcicore_info_t *pi = (pcicore_info_t *)pch;
1473 if (!pcicore_pmecap(pi))
1476 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
1484 pcicore_info_t *pi = (pcicore_info_t *)pch;
1487 if (!pcicore_pmecap(pi))
1490 pcie_war_pmebits(pi);
1491 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
1497 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32),
1506 pcicore_info_t *pi = (pcicore_info_t *)pch;
1509 if (!pcicore_pmecap(pi))
1512 pcie_war_pmebits(pi);
1514 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
1521 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32), w);
1527 pcicore_info_t *pi = (pcicore_info_t *)pch;
1531 osh = pi->osh;
1544 pcicore_info_t *pi = (pcicore_info_t *)pch;
1547 offset = pi->pciecap_lcreg_offset;
1553 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), val);
1555 return OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
1562 pcicore_info_t *pi = (pcicore_info_t *)pch;
1565 pi->sih->pci_pr32414, pi->pcie_polarity, pi->pcie_war_aspm_ovr);
1573 pcicore_info_t *pi = (pcicore_info_t *)pch;
1574 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1578 pcie_writereg(pi->sih, pcieregs, type, offset, val);
1582 if (PCIE_GEN1(pi->sih) &&
1583 pi->sih->buscorerev <= 5 && offset == PCIE_DLLP_PCIE11 && type == PCIE_PCIEREGS)
1586 reg_val = pcie_readreg(pi->sih, pcieregs, type, offset);
1596 pcicore_info_t *pi = (pcicore_info_t *)pch;
1599 pcie_mdiowrite(pi, mdioslave, offset, val);
1602 if (pcie_mdioread(pi, mdioslave, offset, ®_val))
1625 pcicore_info_t *pi = (pcicore_info_t *)pch;
1627 uint32 *tmp = (uint32 *)pi->pcie_configspace;
1630 *tmp++ = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
1639 pcicore_info_t *pi = (pcicore_info_t *)pch;
1641 uint32 *tmp = (uint32 *)pi->pcie_configspace;
1648 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), *tmp);
1658 pcicore_info_t *pi = (pcicore_info_t *)pch;
1659 memcpy(buf, pi->pcie_configspace, size);
1666 pcicore_info_t *pi = (pcicore_info_t *)pch;
1667 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1670 data = pcie_readreg(pi->sih, pcieregs, PCIE_CONFIGREGS, pi->pciecap_lcreg_offset);
1678 pcicore_info_t *pi = (pcicore_info_t *)pch;
1679 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1684 w = (R_REG(pi->osh, (&pcieregs->control)) & ~mask) | val;
1685 W_REG(pi->osh, (&pcieregs->control), w);
1688 return R_REG(pi->osh, (&pcieregs->control));
1700 pcicore_info_t *pi = (pcicore_info_t *)pch;
1702 if (!PCIE_GEN1(pi->sih) && !PCIE_GEN2(pi->sih))