Lines Matching defs:REGISTERS
330 #define REGISTERS ((CPU)->registers)
332 #define GPR (®ISTERS[0])
333 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
335 #define LO (REGISTERS[33])
336 #define HI (REGISTERS[34])
338 #define PC (REGISTERS[PCIDX])
339 #define CAUSE (REGISTERS[36])
341 #define SR (REGISTERS[SRIDX]) /* CPU status register */
343 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
345 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
347 #define Debug (REGISTERS[86])
348 #define DEPC (REGISTERS[87])
349 #define EPC (REGISTERS[88])
350 #define ACX (REGISTERS[89])
361 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
362 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
365 #define DSPCR (REGISTERS[DSPCRIDX])
411 #define ZERO (REGISTERS[0])
412 #define V0 (REGISTERS[2])
413 #define A0 (REGISTERS[4])
414 #define A1 (REGISTERS[5])
415 #define A2 (REGISTERS[6])
416 #define A3 (REGISTERS[7])
418 #define T8 (REGISTERS[T8IDX])
420 #define SP (REGISTERS[SPIDX])
422 #define RA (REGISTERS[RAIDX])