Lines Matching refs:state
77 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
78 a = state->words[1]; \
87 flag = BIT (state->words[0], 8); \
88 state->nullifyMode = BITS (state->words[0], 5, 6); \
89 cond = BITS (state->words[0], 0, 4); \
98 cond = BITS (state->words[0], 0, 4); \
117 field = FIELDD (state->words[0]); \
125 fieldA = FIELDA (state->words[0]); \
137 fieldB = FIELDB (state->words[0]); \
145 fieldC = FIELDC (state->words[0]); \
164 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
167 #define NEXT_WORD(x) (offset += 4, state->words[x])
169 #define add_target(x) (state->targets[state->tcnt++] = (x))
174 core_reg_name (struct arcDisState * state, int val)
176 if (state->coreRegName)
177 return (*state->coreRegName)(state->_this, val);
182 aux_reg_name (struct arcDisState * state, int val)
184 if (state->auxRegName)
185 return (*state->auxRegName)(state->_this, val);
190 cond_code_name (struct arcDisState * state, int val)
192 if (state->condCodeName)
193 return (*state->condCodeName)(state->_this, val);
198 instruction_name (struct arcDisState * state,
203 if (state->instName)
204 return (*state->instName)(state->_this, op1, op2, flags);
209 mwerror (struct arcDisState * state, const char * msg)
211 if (state->err != 0)
212 (*state->err)(state->_this, (msg));
216 post_address (struct arcDisState * state, int addr)
218 static char id[3 * ARRAY_SIZE (state->addresses)];
219 int j, i = state->acnt;
221 if (i < ((int) ARRAY_SIZE (state->addresses)))
223 state->addresses[i] = addr;
224 ++state->acnt;
236 arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
351 ext = core_reg_name (state, val);
381 ext = aux_reg_name (state, val);
385 arc_sprintf (state, bp, "%h", val);
411 write_comments_(struct arcDisState * state,
416 if (state->commentBuffer != 0)
422 const char *name = post_address (state, limm_value + shimm);
427 for (i = 0; i < state->commNum; i++)
430 strcpy (state->commentBuffer, comment_prefix);
432 strcat (state->commentBuffer, ", ");
433 strncat (state->commentBuffer, state->comm[i],
434 sizeof (state->commentBuffer));
439 #define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
450 write_instr_name_(struct arcDisState * state,
459 strcpy (state->instrBuffer, instrName);
466 strcat (state->instrBuffer, ".");
471 cc = cond_code_name (state, cond);
476 strcat (state->instrBuffer, cc);
480 strcat (state->instrBuffer, ".f");
482 switch (state->nullifyMode)
485 strcat (state->instrBuffer, ".d");
488 strcat (state->instrBuffer, ".jd");
493 strcat (state->instrBuffer, ".x");
496 strcat (state->instrBuffer, ".a");
499 strcat (state->instrBuffer, ".di");
505 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
522 dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
549 state->instructionLen = 4;
550 state->nullifyMode = BR_exec_when_no_jump;
551 state->opWidth = 12;
552 state->isBranch = 0;
554 state->_mem_load = 0;
555 state->_ea_present = 0;
556 state->_load_len = 0;
557 state->ea_reg1 = no_reg;
558 state->ea_reg2 = no_reg;
559 state->_offset = 0;
564 state->_opcode = OPCODE (state->words[0]);
569 state->commNum = 0;
570 state->tcnt = 0;
571 state->acnt = 0;
572 state->flow = noflow;
575 if (state->commentBuffer)
576 state->commentBuffer[0] = '\0';
578 switch (state->_opcode)
581 switch (BITS (state->words[0],1,2))
585 state->_load_len = 4;
589 state->_load_len = 1;
593 state->_load_len = 2;
597 state->flow = invalid_instr;
604 if (BIT (state->words[0],13))
611 switch (BITS (state->words[0], 10, 11))
615 state->_load_len = 4;
619 state->_load_len = 1;
623 state->_load_len = 2;
627 state->flow = invalid_instr;
635 if (BIT (state->words[0], 25))
642 switch (BITS (state->words[0], 22, 23))
655 state->flow = invalid_instr;
664 switch (FIELDC (state->words[0]))
697 switch (FIELDD (state->words[0]))
710 state->flow=invalid_instr;
719 instrName = instruction_name (state,
720 state->_opcode,
721 FIELDC (state->words[0]),
726 state->flow = invalid_instr;
745 if (BITS (state->words[0],9,9))
757 decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH );
758 state->isBranch = 1;
764 repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
766 switch (state->_opcode)
790 if (state->words[0] == 0x7fffffff)
801 instrName = instruction_name (state,state->_opcode,0,&flags);
806 state->flow=invalid_instr;
815 state->nullifyMode = BR_exec_when_no_jump; /* 0 */
836 arc_sprintf (state, state->operandBuffer, formatString,
844 arc_sprintf (state, state->operandBuffer, formatString,
861 arc_sprintf (state, state->operandBuffer, formatString,
867 arc_sprintf (state, state->operandBuffer, formatString, fieldB);
879 arc_sprintf (state, state->operandBuffer, formatString, fieldB);
884 fieldA = BITS (state->words[0],7,26) << 2;
892 if (state->_opcode != op_LPC /* LP */)
895 state->flow = state->_opcode == op_BLC /* BL */
903 arc_sprintf (state, state->operandBuffer, formatString,
904 post_address (state, fieldA));
921 state->flow = is_linked ? direct_call : direct_jump;
925 if (is_linked && state->nullifyMode == BR_exec_when_jump)
926 state->nullifyMode = BR_exec_when_no_jump;
930 state->flow = is_linked ? indirect_call : indirect_jump;
935 state->register_for_indirect_jump = fieldB;
947 arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
949 arc_sprintf (state, state->operandBuffer, formatString,
950 post_address (state, fieldB), fieldA);
963 state->_offset = 0;
964 state->_ea_present = 1;
966 state->ea_reg1 = fieldB;
968 state->_offset += fieldB;
970 state->ea_reg2 = fieldC;
972 state->_offset += fieldC;
973 state->_mem_load = 1;
975 directMem = BIT (state->words[0], 5);
976 addrWriteBack = BIT (state->words[0], 3);
977 signExtend = BIT (state->words[0], 0);
987 arc_sprintf (state, state->operandBuffer, formatString,
996 fieldC = FIELDD (state->words[0]);
1001 state->_ea_present = 1;
1002 state->_offset = fieldC;
1003 state->_mem_load = 1;
1005 state->ea_reg1 = fieldB;
1009 state->_offset += fieldB, state->_ea_present = 0;
1011 directMem = BIT (state->words[0],14);
1012 addrWriteBack = BIT (state->words[0],12);
1013 signExtend = BIT (state->words[0],9);
1019 fieldB = state->_offset;
1025 if (fieldC != 0 && !BIT (state->words[0],13))
1033 arc_sprintf (state, state->operandBuffer, formatString,
1042 fieldA = FIELDD(state->words[0]); /* shimm */
1047 state->_ea_present = 1;
1048 state->_offset = fieldA;
1050 state->ea_reg1 = fieldB;
1055 state->_offset += fieldB, state->_ea_present = 0;
1057 directMem = BIT (state->words[0], 26);
1058 addrWriteBack = BIT (state->words[0], 24);
1065 fieldB = state->_offset;
1079 arc_sprintf (state, state->operandBuffer, formatString,
1095 arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
1101 state->operandBuffer[0] = '\0';
1115 arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
1120 mwerror (state, "Bad decoding class in ARC disassembler");
1124 state->_cond = cond;
1125 return state->instructionLen = offset;
1170 struct arcDisState s; /* ARC Disassembler state. */