Lines Matching refs:regm3
803 if (cinfo->regm3 > REGM3_MAX)
831 if (cinfo->regm3 > 0)
832 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
909 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
910 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
911 ++cur.regm3) {
913 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
992 dsi.current_cinfo.regm3 = cinfo->regm3;
1015 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1016 cinfo->regm3, cinfo->dsi1_pll_fclk);
1026 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1177 cinfo->regm3,
2950 cinfo.regm3 = dssdev->phy.dsi.div.regm3;