Lines Matching refs:plane
75 /* DISPC GFX plane */
98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
542 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
544 BUG_ON(plane == OMAP_DSS_GFX);
546 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
549 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
551 BUG_ON(plane == OMAP_DSS_GFX);
553 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
556 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
558 BUG_ON(plane == OMAP_DSS_GFX);
560 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
563 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
704 _dispc_write_firh_reg(plane, i, h);
705 _dispc_write_firhv_reg(plane, i, hv);
714 _dispc_write_firv_reg(plane, i, v);
752 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
758 dispc_write_reg(ba0_reg[plane], paddr);
761 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
767 dispc_write_reg(ba1_reg[plane], paddr);
770 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
777 dispc_write_reg(pos_reg[plane], val);
780 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
786 dispc_write_reg(siz_reg[plane], val);
789 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
795 BUG_ON(plane == OMAP_DSS_GFX);
798 dispc_write_reg(vsi_reg[plane-1], val);
801 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
804 BUG_ON(plane == OMAP_DSS_VIDEO1);
809 if (plane == OMAP_DSS_GFX)
811 else if (plane == OMAP_DSS_VIDEO2)
815 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
821 dispc_write_reg(ri_reg[plane], inc);
824 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
830 dispc_write_reg(ri_reg[plane], inc);
833 static void _dispc_set_color_mode(enum omap_plane plane,
871 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
874 static void _dispc_set_channel_out(enum omap_plane plane,
880 switch (plane) {
893 val = dispc_read_reg(dispc_reg_att[plane]);
895 dispc_write_reg(dispc_reg_att[plane], val);
898 void dispc_set_burst_size(enum omap_plane plane,
906 switch (plane) {
919 val = dispc_read_reg(dispc_reg_att[plane]);
921 dispc_write_reg(dispc_reg_att[plane], val);
926 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
930 BUG_ON(plane == OMAP_DSS_GFX);
932 val = dispc_read_reg(dispc_reg_att[plane]);
934 dispc_write_reg(dispc_reg_att[plane], val);
937 void dispc_enable_replication(enum omap_plane plane, bool enable)
941 if (plane == OMAP_DSS_GFX)
947 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
977 int plane;
981 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
983 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
985 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
989 dispc.fifo_size[plane] = size;
995 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
997 return dispc.fifo_size[plane];
1000 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1008 plane,
1009 REG_GET(ftrs_reg[plane], 11, 0),
1010 REG_GET(ftrs_reg[plane], 27, 16),
1014 dispc_write_reg(ftrs_reg[plane],
1017 dispc_write_reg(ftrs_reg[plane],
1033 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1039 BUG_ON(plane == OMAP_DSS_GFX);
1045 dispc_write_reg(fir_reg[plane-1], val);
1048 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1054 BUG_ON(plane == OMAP_DSS_GFX);
1057 dispc_write_reg(ac0_reg[plane-1], val);
1060 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1066 BUG_ON(plane == OMAP_DSS_GFX);
1069 dispc_write_reg(ac1_reg[plane-1], val);
1073 static void _dispc_set_scaling(enum omap_plane plane,
1086 BUG_ON(plane == OMAP_DSS_GFX);
1091 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1103 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1105 l = dispc_read_reg(dispc_reg_att[plane]);
1117 dispc_write_reg(dispc_reg_att[plane], l);
1132 _dispc_set_vid_accu0(plane, 0, accu0);
1133 _dispc_set_vid_accu1(plane, 0, accu1);
1136 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1175 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1178 REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1180 REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1182 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1183 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1508 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1511 _dispc_set_channel_out(plane, channel_out);
1515 static int _dispc_setup_plane(enum omap_plane plane,
1553 if (plane == OMAP_DSS_GFX) {
1575 /* video plane */
1603 if (plane == OMAP_DSS_VIDEO1)
1682 _dispc_set_color_mode(plane, color_mode);
1684 _dispc_set_plane_ba0(plane, paddr + offset0);
1685 _dispc_set_plane_ba1(plane, paddr + offset1);
1687 _dispc_set_row_inc(plane, row_inc);
1688 _dispc_set_pix_inc(plane, pix_inc);
1693 _dispc_set_plane_pos(plane, pos_x, pos_y);
1695 _dispc_set_pic_size(plane, width, height);
1697 if (plane != OMAP_DSS_GFX) {
1698 _dispc_set_scaling(plane, width, height,
1701 _dispc_set_vid_size(plane, out_width, out_height);
1702 _dispc_set_vid_color_conv(plane, cconv);
1705 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1707 if (plane != OMAP_DSS_VIDEO1)
1708 _dispc_setup_global_alpha(plane, global_alpha);
1713 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1715 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
3130 int dispc_enable_plane(enum omap_plane plane, bool enable)
3132 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3135 _dispc_enable_plane(plane, enable);
3141 int dispc_setup_plane(enum omap_plane plane,
3155 plane, paddr, screen_width, pos_x, pos_y,
3163 r = _dispc_setup_plane(plane,