Lines Matching refs:dpll
675 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
681 if (dpll & DPLL_P1_FORCE_DIV2)
684 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
688 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
690 if (dpll & DPLL_P1_FORCE_DIV2)
693 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
694 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
1033 u32 *dpll, *fp0, *fp1;
1048 dpll = &hw->dpll_b;
1060 dpll = &hw->dpll_a;
1096 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1097 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1098 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1121 *dpll &= ~DPLL_P1_FORCE_DIV2;
1122 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1126 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1127 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1129 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1270 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1292 dpll = &hw->dpll_b;
1316 dpll = &hw->dpll_a;
1396 OUTREG(dpll_reg, *dpll);