Lines Matching refs:aty_ld_le32
515 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
532 return aty_ld_le32(CLOCK_CNTL_DATA);
583 val = aty_ld_le32(BIOS_0_SCRATCH);
586 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
589 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
607 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
624 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
648 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
654 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
665 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
670 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
672 aty_ld_le32(GEN_RESET_CNTL);
674 aty_ld_le32(GEN_RESET_CNTL);
786 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
790 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
957 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
1245 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1246 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1248 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1259 reg = aty_ld_le32(LVDS_GEN_CNTL);
1270 reg = aty_ld_le32(LVDS_GEN_CNTL);
1287 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1472 config = aty_ld_le32(CNFG_CNTL) & ~3;
1610 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1717 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1733 aty_ld_le32(LVDS_GEN_CNTL);
1746 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1754 aty_ld_le32(LVDS_GEN_CNTL);
1760 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1864 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1965 dac = aty_ld_le32(DAC_CNTL);
1973 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2053 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2314 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &