Lines Matching defs:FlashReg
55 void __iomem *FlashReg;
141 FlashReg + intr_status[i]);
144 iowrite32(device_reset_banks[i], FlashReg + DEVICE_RESET);
145 while (!(ioread32(FlashReg + intr_status[i]) &
148 if (ioread32(FlashReg + intr_status[i]) &
156 FlashReg + intr_status[i]);
245 if ((ioread32(FlashReg + MANUFACTURER_ID) == 0) &&
246 (ioread32(FlashReg + DEVICE_ID) == 0x88))
249 iowrite32(acc_clks, FlashReg + ACC_CLKS);
250 iowrite32(re_2_we, FlashReg + RE_2_WE);
251 iowrite32(re_2_re, FlashReg + RE_2_RE);
252 iowrite32(we_2_re, FlashReg + WE_2_RE);
253 iowrite32(addr_2_data, FlashReg + ADDR_2_DATA);
254 iowrite32(en_lo, FlashReg + RDWR_EN_LO_CNT);
255 iowrite32(en_hi, FlashReg + RDWR_EN_HI_CNT);
256 iowrite32(cs_cnt, FlashReg + CS_SETUP_CNT);
274 if ((ioread32(FlashReg + DEVICE_MAIN_AREA_SIZE) < 4096) ||
275 (ioread32(FlashReg + DEVICE_SPARE_AREA_SIZE) <= 128))
276 iowrite32(8, FlashReg + ECC_CORRECTION);
279 if ((ioread32(FlashReg + ECC_CORRECTION) & ECC_CORRECTION__VALUE)
291 (ioread32(FlashReg + ECC_CORRECTION) &
313 iowrite32(DEVICE_RESET__BANK0, FlashReg + DEVICE_RESET);
315 while (!((ioread32(FlashReg + INTR_STATUS0) &
317 (ioread32(FlashReg + INTR_STATUS0) &
321 if (ioread32(FlashReg + INTR_STATUS0) & INTR_STATUS0__RST_COMP) {
322 iowrite32(DEVICE_RESET__BANK1, FlashReg + DEVICE_RESET);
323 while (!((ioread32(FlashReg + INTR_STATUS1) &
325 (ioread32(FlashReg + INTR_STATUS1) &
329 if (ioread32(FlashReg + INTR_STATUS1) &
332 FlashReg + DEVICE_RESET);
333 while (!((ioread32(FlashReg + INTR_STATUS2) &
335 (ioread32(FlashReg + INTR_STATUS2) &
339 if (ioread32(FlashReg + INTR_STATUS2) &
342 FlashReg + DEVICE_RESET);
343 while (!((ioread32(FlashReg + INTR_STATUS3) &
345 (ioread32(FlashReg + INTR_STATUS3) &
356 iowrite32(INTR_STATUS0__TIME_OUT, FlashReg + INTR_STATUS0);
357 iowrite32(INTR_STATUS1__TIME_OUT, FlashReg + INTR_STATUS1);
358 iowrite32(INTR_STATUS2__TIME_OUT, FlashReg + INTR_STATUS2);
359 iowrite32(INTR_STATUS3__TIME_OUT, FlashReg + INTR_STATUS3);
362 ioread32(FlashReg + ONFI_DEVICE_FEATURES);
364 ioread32(FlashReg + ONFI_OPTIONAL_COMMANDS);
366 ioread32(FlashReg + ONFI_TIMING_MODE);
368 ioread32(FlashReg + ONFI_PGM_CACHE_TIMING_MODE);
370 n_of_luns = ioread32(FlashReg + ONFI_DEVICE_NO_OF_LUNS) &
372 blks_lun_l = ioread32(FlashReg + ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L);
373 blks_lun_h = ioread32(FlashReg + ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U);
379 if (!(ioread32(FlashReg + ONFI_TIMING_MODE) &
384 if (ioread32(FlashReg + ONFI_TIMING_MODE) & (0x01 << i))
402 /* iowrite32(1, FlashReg + CACHE_WRITE_ENABLE); */
403 /* iowrite32(1, FlashReg + CACHE_READ_ENABLE); */
428 iowrite32(5, FlashReg + ACC_CLKS);
429 iowrite32(20, FlashReg + RE_2_WE);
430 iowrite32(12, FlashReg + WE_2_RE);
431 iowrite32(14, FlashReg + ADDR_2_DATA);
432 iowrite32(3, FlashReg + RDWR_EN_LO_CNT);
433 iowrite32(2, FlashReg + RDWR_EN_HI_CNT);
434 iowrite32(2, FlashReg + CS_SETUP_CNT);
439 blk_size = 64 << ((ioread32(FlashReg + DEVICE_PARAM_1) & 0x30) >> 4);
451 if ((ioread32(FlashReg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
452 (ioread32(FlashReg + DEVICE_SPARE_AREA_SIZE) == 64)) {
453 iowrite32(216, FlashReg + DEVICE_SPARE_AREA_SIZE);
454 tmp = ioread32(FlashReg + DEVICES_CONNECTED) *
455 ioread32(FlashReg + DEVICE_SPARE_AREA_SIZE);
456 iowrite32(tmp, FlashReg + LOGICAL_PAGE_SPARE_SIZE);
458 iowrite32(15, FlashReg + ECC_CORRECTION);
460 iowrite32(8, FlashReg + ECC_CORRECTION);
492 iowrite32(128, FlashReg + PAGES_PER_BLOCK);
493 iowrite32(4096, FlashReg + DEVICE_MAIN_AREA_SIZE);
494 iowrite32(224, FlashReg + DEVICE_SPARE_AREA_SIZE);
495 main_size = 4096 * ioread32(FlashReg + DEVICES_CONNECTED);
496 spare_size = 224 * ioread32(FlashReg + DEVICES_CONNECTED);
497 iowrite32(main_size, FlashReg + LOGICAL_PAGE_DATA_SIZE);
498 iowrite32(spare_size, FlashReg + LOGICAL_PAGE_SPARE_SIZE);
499 iowrite32(0, FlashReg + DEVICE_WIDTH);
501 iowrite32(15, FlashReg + ECC_CORRECTION);
503 iowrite32(8, FlashReg + ECC_CORRECTION);
560 if (ioread32(FlashReg + FEATURES) & FEATURES__PARTITION) {
561 if ((ioread32(FlashReg + PERM_SRC_ID_1) &
564 ((ioread32(FlashReg + MIN_MAX_BANK_1) &
568 (ioread32(FlashReg + MIN_BLK_ADDR_1) &
572 (((ioread32(FlashReg + MIN_MAX_BANK_1) &
576 (ioread32(FlashReg + MAX_BLK_ADDR_1) &
684 iowrite32(0x02, FlashReg + SPARE_AREA_SKIP_BYTES);
685 iowrite32(0xffff, FlashReg + SPARE_AREA_MARKER);
686 DeviceInfo.wDeviceMaker = ioread32(FlashReg + MANUFACTURER_ID);
687 DeviceInfo.wDeviceID = ioread32(FlashReg + DEVICE_ID);
688 DeviceInfo.MLCDevice = ioread32(FlashReg + DEVICE_PARAM_0) & 0x0c;
690 if (ioread32(FlashReg + ONFI_DEVICE_NO_OF_LUNS) &
708 ioread32(FlashReg + ACC_CLKS),
709 ioread32(FlashReg + RE_2_WE),
710 ioread32(FlashReg + WE_2_RE),
711 ioread32(FlashReg + ADDR_2_DATA),
712 ioread32(FlashReg + RDWR_EN_LO_CNT),
713 ioread32(FlashReg + RDWR_EN_HI_CNT),
714 ioread32(FlashReg + CS_SETUP_CNT));
716 DeviceInfo.wHWRevision = ioread32(FlashReg + REVISION);
717 DeviceInfo.wHWFeatures = ioread32(FlashReg + FEATURES);
720 ioread32(FlashReg + DEVICE_MAIN_AREA_SIZE);
722 ioread32(FlashReg + DEVICE_SPARE_AREA_SIZE);
725 ioread32(FlashReg + LOGICAL_PAGE_DATA_SIZE);
735 ioread32(FlashReg + LOGICAL_PAGE_SPARE_SIZE);
737 DeviceInfo.wPagesPerBlock = ioread32(FlashReg + PAGES_PER_BLOCK);
746 DeviceInfo.wDeviceWidth = ioread32(FlashReg + DEVICE_WIDTH);
748 ((ioread32(FlashReg + DEVICE_WIDTH) > 0) ? 16 : 8);
750 DeviceInfo.wDevicesConnected = ioread32(FlashReg + DEVICES_CONNECTED);
753 ioread32(FlashReg + SPARE_AREA_SKIP_BYTES) *
765 no_of_planes = ioread32(FlashReg + NUMBER_OF_PLANES) &
813 iowrite32(1, FlashReg + GLOBAL_INT_ENABLE);
815 iowrite32(0, FlashReg + GLOBAL_INT_ENABLE);
842 FlashReg + intr_status);
847 while (!(ioread32(FlashReg + intr_status) &
851 if (ioread32(FlashReg + intr_status) &
856 FlashReg + intr_status);
913 iowrite32(ioread32(FlashReg + intr_status),
914 FlashReg + intr_status);
922 while (!(ioread32(FlashReg + intr_status) &
1032 err_page = ioread32(FlashReg + err_page_addr[bank]);
1033 err_addr = ioread32(FlashReg + ECC_ERROR_ADDRESS);
1036 err_fix_info = ioread32(FlashReg + ERR_CORRECTION_INFO);
1048 ioread32(FlashReg + PTN_INTR),
1112 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1115 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1120 if (ioread32(FlashReg + MULTIPLANE_OPERATION))
1136 if (ioread32(FlashReg + MULTIPLANE_OPERATION))
1146 iowrite32(1, FlashReg + DMA_ENABLE);
1147 while (!(ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1150 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1151 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1156 while (!(ioread32(FlashReg + intr_status) &
1161 if (ioread32(FlashReg + intr_status) &
1164 FlashReg + intr_status);
1169 if (ioread32(FlashReg + intr_status) &
1174 FlashReg + intr_status);
1175 else if (ioread32(FlashReg + intr_status) &
1178 FlashReg + intr_status);
1179 else if (ioread32(FlashReg + intr_status) &
1182 FlashReg + intr_status);
1184 while (!(ioread32(FlashReg + intr_status) &
1187 iowrite32(INTR_STATUS0__DMA_CMD_COMP, FlashReg + intr_status);
1190 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1192 iowrite32(0, FlashReg + DMA_ENABLE);
1193 while ((ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1227 iowrite32(ioread32(FlashReg + intr_status),
1228 FlashReg + intr_status);
1230 iowrite32(1, FlashReg + DMA_ENABLE);
1231 while (!(ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1234 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1243 while (!ioread32(FlashReg + intr_status))
1246 if (ioread32(FlashReg + intr_status) &
1249 FlashReg + intr_status);
1252 } else if (ioread32(FlashReg + intr_status) &
1255 FlashReg + intr_status);
1261 } else if (ioread32(FlashReg + intr_status) &
1265 FlashReg + intr_status);
1273 while (!(ioread32(FlashReg + intr_status) &
1278 FlashReg + intr_status);
1285 FlashReg + intr_status);
1289 iowrite32(ioread32(FlashReg + intr_status),
1290 FlashReg + intr_status);
1292 iowrite32(0, FlashReg + DMA_ENABLE);
1294 while ((ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1324 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1327 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1332 if (ioread32(FlashReg + MULTIPLANE_OPERATION))
1348 if (ioread32(FlashReg + MULTIPLANE_OPERATION))
1358 iowrite32(1, FlashReg + DMA_ENABLE);
1359 while (!(ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1362 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1363 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1375 iowrite32(1, FlashReg + GLOBAL_INT_ENABLE); /* Enable Interrupt */
1386 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1388 iowrite32(0, FlashReg + DMA_ENABLE);
1389 while ((ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1522 iowrite32(ioread32(FlashReg + intr_status),
1523 FlashReg + intr_status);
1525 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1526 iowrite32(0x01, FlashReg + MULTIPLANE_OPERATION);
1528 iowrite32(1, FlashReg + DMA_ENABLE);
1529 while (!(ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1538 while (!ioread32(FlashReg + intr_status))
1541 if (ioread32(FlashReg + intr_status) &
1544 FlashReg + intr_status);
1547 } else if (ioread32(FlashReg + intr_status) &
1550 FlashReg + intr_status);
1556 } else if (ioread32(FlashReg + intr_status) &
1560 FlashReg + intr_status);
1568 while (!(ioread32(FlashReg + intr_status) &
1572 FlashReg + intr_status);
1579 FlashReg + intr_status);
1583 iowrite32(ioread32(FlashReg + intr_status),
1584 FlashReg + intr_status);
1586 iowrite32(0, FlashReg + DMA_ENABLE);
1588 while ((ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1591 iowrite32(0, FlashReg + MULTIPLANE_OPERATION);
1627 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1629 iowrite32(1, FlashReg + DMA_ENABLE);
1630 while (!(ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1633 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1648 iowrite32(1, FlashReg + GLOBAL_INT_ENABLE); /* Enable Interrupt */
1659 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1661 iowrite32(0, FlashReg + DMA_ENABLE);
1663 while ((ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1697 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1700 INTR_STATUS0__PROGRAM_FAIL, FlashReg + intr_status);
1705 if (ioread32(FlashReg + MULTIPLANE_OPERATION))
1720 if (ioread32(FlashReg + MULTIPLANE_OPERATION))
1730 iowrite32(1, FlashReg + DMA_ENABLE);
1731 while (!(ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
1734 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1736 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1748 iowrite32(1, FlashReg + GLOBAL_INT_ENABLE); /* Enable interrupt */
1759 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
1761 iowrite32(0, FlashReg + DMA_ENABLE);
1762 while (ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG)
1774 iowrite32(1, FlashReg + ECC_ENABLE);
1780 iowrite32(0, FlashReg + ECC_ENABLE);
1815 iowrite32(1, FlashReg + TRANSFER_SPARE_REG);
1823 iowrite32(ioread32(FlashReg + intr_status),
1824 FlashReg + intr_status);
1879 while (!(ioread32(FlashReg + intr_status) &
1884 if (ioread32(FlashReg + intr_status) &
1888 iowrite32(ioread32(FlashReg + intr_status),
1889 FlashReg + intr_status);
1896 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
1934 iowrite32(1, FlashReg + TRANSFER_SPARE_REG);
1936 iowrite32(ioread32(FlashReg + intr_status),
1937 FlashReg + intr_status);
1952 while (!(ioread32(FlashReg + intr_status) &
2004 while (!(ioread32(FlashReg + intr_status) &
2009 if (ioread32(FlashReg + intr_status) &
2012 FlashReg + intr_status);
2017 if (ioread32(FlashReg + intr_status) &
2022 FlashReg + intr_status);
2023 } else if (ioread32(FlashReg + intr_status) &
2027 FlashReg + intr_status);
2028 } else if (ioread32(FlashReg + intr_status) &
2031 FlashReg + intr_status);
2041 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
2079 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
2081 iowrite32(1, FlashReg + DMA_ENABLE);
2082 while (!(ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
2085 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
2100 iowrite32(1, FlashReg + GLOBAL_INT_ENABLE); /* Enable interrupt */
2111 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
2113 iowrite32(0, FlashReg + DMA_ENABLE);
2114 while ((ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
2148 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
2150 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
2151 iowrite32(0x01, FlashReg + MULTIPLANE_OPERATION);
2153 iowrite32(1, FlashReg + DMA_ENABLE);
2154 while (!(ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
2157 iowrite32(0, FlashReg + TRANSFER_SPARE_REG);
2165 while (!ioread32(FlashReg + intr_status))
2168 if (ioread32(FlashReg + intr_status) &
2171 FlashReg + intr_status);
2176 } else if (ioread32(FlashReg + intr_status) &
2180 t = ioread32(FlashReg + intr_status) &
2182 iowrite32(t, FlashReg + intr_status);
2186 FlashReg + intr_status);
2190 iowrite32(ioread32(FlashReg + intr_status), FlashReg + intr_status);
2192 iowrite32(0, FlashReg + DMA_ENABLE);
2194 while ((ioread32(FlashReg + DMA_ENABLE) & DMA_ENABLE__FLAG))
2197 iowrite32(0, FlashReg + MULTIPLANE_OPERATION);
2216 iowrite32(0, FlashReg + GLOBAL_INT_ENABLE);
2238 if (ioread32(FlashReg + intr_status) &
2241 FlashReg + intr_status);
2245 } else if (ioread32(FlashReg + intr_status) &
2248 FlashReg + intr_status);
2252 } else if (ioread32(FlashReg + intr_status) &
2255 FlashReg + intr_status);
2261 if (ioread32(FlashReg + intr_status) &
2264 FlashReg + intr_status);
2270 ioread32(FlashReg + intr_status));
2277 FlashReg + intr_status);
2295 while (!ioread32(FlashReg + intr_status))
2298 if (ioread32(FlashReg + intr_status) &
2301 FlashReg + intr_status);
2305 } else if (ioread32(FlashReg + intr_status) &
2309 FlashReg + intr_status);
2313 FlashReg + intr_status);
2331 ints0 = ioread32(FlashReg + INTR_STATUS0);
2332 ints1 = ioread32(FlashReg + INTR_STATUS1);
2333 ints2 = ioread32(FlashReg + INTR_STATUS2);
2334 ints3 = ioread32(FlashReg + INTR_STATUS3);
2343 ioread32(FlashReg + DMA_INTR),
2346 if (!(ioread32(FlashReg + ints_offset) & int_mask)) {
2347 iowrite32(ints0, FlashReg + INTR_STATUS0);
2348 iowrite32(ints1, FlashReg + INTR_STATUS1);
2349 iowrite32(ints2, FlashReg + INTR_STATUS2);
2350 iowrite32(ints3, FlashReg + INTR_STATUS3);
2361 iowrite32(0, FlashReg + GLOBAL_INT_ENABLE);
2366 iowrite32(0, FlashReg + GLOBAL_INT_ENABLE);
2502 FlashReg = ioremap_nocache(GLOB_HWCTL_REG_BASE,
2504 if (!FlashReg) {
2511 FlashReg, GLOB_HWCTL_REG_SIZE);
2517 iounmap(FlashReg);
2529 ioread32(FlashReg + ACC_CLKS),
2530 ioread32(FlashReg + RE_2_WE),
2531 ioread32(FlashReg + WE_2_RE),
2532 ioread32(FlashReg + ADDR_2_DATA),
2533 ioread32(FlashReg + RDWR_EN_LO_CNT),
2534 ioread32(FlashReg + RDWR_EN_HI_CNT),
2535 ioread32(FlashReg + CS_SETUP_CNT));
2539 iowrite32(0, FlashReg + GLOBAL_INT_ENABLE);
2550 iowrite32(int_mask, FlashReg + DMA_INTR_EN);
2551 iowrite32(0xFFFF, FlashReg + DMA_INTR);
2563 iowrite32(int_mask, FlashReg + INTR_EN0);
2564 iowrite32(int_mask, FlashReg + INTR_EN1);
2565 iowrite32(int_mask, FlashReg + INTR_EN2);
2566 iowrite32(int_mask, FlashReg + INTR_EN3);
2569 iowrite32(0xFFFF, FlashReg + INTR_STATUS0);
2570 iowrite32(0xFFFF, FlashReg + INTR_STATUS1);
2571 iowrite32(0xFFFF, FlashReg + INTR_STATUS2);
2572 iowrite32(0xFFFF, FlashReg + INTR_STATUS3);
2574 iowrite32(0x0F, FlashReg + RB_PIN_ENABLED);
2575 iowrite32(CHIP_EN_DONT_CARE__FLAG, FlashReg + CHIP_ENABLE_DONT_CARE);
2578 iowrite32(0, FlashReg + TWO_ROW_ADDR_CYCLES);
2579 iowrite32(1, FlashReg + ECC_ENABLE);
2594 iounmap(FlashReg);