Lines Matching refs:timer_base
97 uint32 timer_base = LCDC_BASE;
231 timer_base = DTV_BASE;
249 MDP_OUTP(MDP_BASE + timer_base + 0x4, hsync_ctrl);
250 MDP_OUTP(MDP_BASE + timer_base + 0x8, vsync_period);
251 MDP_OUTP(MDP_BASE + timer_base + 0xc, vsync_pulse_width * hsync_period);
252 if (timer_base == LCDC_BASE) {
253 MDP_OUTP(MDP_BASE + timer_base + 0x10, display_hctl);
254 MDP_OUTP(MDP_BASE + timer_base + 0x14, display_v_start);
255 MDP_OUTP(MDP_BASE + timer_base + 0x18, display_v_end);
256 MDP_OUTP(MDP_BASE + timer_base + 0x28, lcdc_border_clr);
257 MDP_OUTP(MDP_BASE + timer_base + 0x2c, lcdc_underflow_clr);
258 MDP_OUTP(MDP_BASE + timer_base + 0x30, lcdc_hsync_skew);
259 MDP_OUTP(MDP_BASE + timer_base + 0x38, ctrl_polarity);
260 MDP_OUTP(MDP_BASE + timer_base + 0x1c, active_hctl);
261 MDP_OUTP(MDP_BASE + timer_base + 0x20, active_v_start);
262 MDP_OUTP(MDP_BASE + timer_base + 0x24, active_v_end);
264 MDP_OUTP(MDP_BASE + timer_base + 0x18, display_hctl);
265 MDP_OUTP(MDP_BASE + timer_base + 0x1c, display_v_start);
266 MDP_OUTP(MDP_BASE + timer_base + 0x20, display_v_end);
267 MDP_OUTP(MDP_BASE + timer_base + 0x40, lcdc_border_clr);
268 MDP_OUTP(MDP_BASE + timer_base + 0x44, lcdc_underflow_clr);
269 MDP_OUTP(MDP_BASE + timer_base + 0x48, lcdc_hsync_skew);
270 MDP_OUTP(MDP_BASE + timer_base + 0x50, ctrl_polarity);
271 MDP_OUTP(MDP_BASE + timer_base + 0x2c, active_hctl);
272 MDP_OUTP(MDP_BASE + timer_base + 0x30, active_v_start);
273 MDP_OUTP(MDP_BASE + timer_base + 0x38, active_v_end);
279 MDP_OUTP(MDP_BASE + timer_base, 1);
292 uint32 timer_base = LCDC_BASE;
300 timer_base = DTV_BASE;
306 MDP_OUTP(MDP_BASE + timer_base, 0);