Lines Matching refs:cc
29 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
33 value |= chipco_read32(cc, offset) & ~mask;
34 chipco_write32(cc, offset, value);
39 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
42 struct ssb_device *ccdev = cc->dev;
55 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
60 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
62 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
66 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
69 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
72 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
78 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
90 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
92 struct ssb_bus *bus = cc->dev->bus;
95 if (cc->dev->id.revision < 6) {
106 if (cc->dev->id.revision < 10) {
107 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
121 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
128 clocksrc = chipco_pctl_get_slowclksrc(cc);
129 if (cc->dev->id.revision < 6) {
140 } else if (cc->dev->id.revision < 10) {
146 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
152 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
182 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
184 struct ssb_bus *bus = cc->dev->bus;
188 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
190 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
193 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
196 if (cc->dev->id.revision >= 10) {
198 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
199 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
204 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
205 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
207 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
213 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
215 struct ssb_bus *bus = cc->dev->bus;
230 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
232 struct ssb_bus *bus = cc->dev->bus;
240 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
241 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
245 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
248 minfreq = chipco_pctl_clockfreqlimit(cc, 0);
249 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
253 cc->fast_pwrup_delay = tmp;
256 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
258 if (!cc->dev)
260 if (cc->dev->id.revision >= 11)
261 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
262 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
263 ssb_pmu_init(cc);
264 chipco_powercontrol_init(cc);
265 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
266 calc_fast_powerup_delay(cc);
269 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
271 if (!cc->dev)
273 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
276 void ssb_chipco_resume(struct ssb_chipcommon *cc)
278 if (!cc->dev)
280 chipco_powercontrol_init(cc);
281 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
285 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
288 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
289 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
295 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
299 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
302 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
308 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
311 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
312 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
315 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
318 if (cc->dev->bus->chip_id != 0x5365) {
319 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
324 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
328 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
331 struct ssb_device *dev = cc->dev;
336 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
340 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
348 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
352 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
360 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
365 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
368 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
371 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
373 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
376 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
378 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
381 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
383 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
386 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
388 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
391 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
393 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
396 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
398 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
402 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
404 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
407 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
409 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
413 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
416 struct ssb_bus *bus = cc->dev->bus;
422 unsigned int ccrev = cc->dev->id.revision;
424 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
425 irq = ssb_mips_irq(cc->dev);
430 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
431 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
439 chipco_write32(cc, SSB_CHIPCO_CORECTL,
440 chipco_read32(cc, SSB_CHIPCO_CORECTL)
445 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
451 chipco_write32(cc, SSB_CHIPCO_CORECTL,
452 chipco_read32(cc, SSB_CHIPCO_CORECTL)
456 chipco_write32(cc, SSB_CHIPCO_CORECTL,
457 chipco_read32(cc, SSB_CHIPCO_CORECTL)
461 chipco_write32(cc, SSB_CHIPCO_CORECTL,
462 chipco_read32(cc, SSB_CHIPCO_CORECTL)
468 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
478 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
479 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
491 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
496 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);