Lines Matching defs:sci
185 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
201 } while (TX_FIFO_LVL(val, sci) && loops--);
210 if (RX_FIFO_LVL(val, sci))
236 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
279 if (sci->high_speed && sdd->cur_speed >= 30000000UL
322 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
339 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
358 while ((TX_FIFO_LVL(status, sci)
359 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
571 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
618 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
799 struct s3c64xx_spi_info *sci;
811 sci = sdd->cntrlr_info;
880 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
891 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
915 struct s3c64xx_spi_info *sci;
930 sci = pdev->dev.platform_data;
931 if (!sci->src_clk_name) {
968 sdd->cntrlr_info = sci;
979 master->num_chipselect = sci->num_cs;
998 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
1018 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1021 "Unable to acquire clock '%s'\n", sci->src_clk_name);
1028 sci->src_clk_name);
1149 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1152 sci->cfg_gpio(pdev);