Lines Matching refs:up
270 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
273 if (!ZS_REGS_HELD(up)) {
274 if (ZS_TX_ACTIVE(up)) {
275 up->flags |= SUNZILOG_FLAG_REGS_HELD;
277 __load_zsregs(channel, up->curregs);
282 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
284 unsigned int cur_cflag = up->cflag;
287 up->cflag &= ~CBAUD;
288 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
291 up->curregs[R12] = (brg & 0xff);
292 up->curregs[R13] = (brg >> 8) & 0xff;
293 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
296 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
299 if (ZS_IS_KEYB(up)) {
302 if (up->serio_open)
303 serio_interrupt(&up->serio, ch, 0);
305 } else if (ZS_IS_MOUSE(up)) {
310 sunzilog_change_mouse_baud(up);
317 if (up->serio_open)
318 serio_interrupt(&up->serio, ch, 0);
326 sunzilog_receive_chars(struct uart_sunzilog_port *up,
333 if (up->port.state != NULL && /* Unopened serial console */
334 up->port.state->port.tty != NULL) /* Keyboard || mouse */
335 tty = up->port.state->port.tty;
361 ch &= up->parity_mask;
363 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
364 sunzilog_kbdms_receive_chars(up, ch, 0);
369 uart_handle_sysrq_char(&up->port, ch);
375 up->port.icount.rx++;
379 up->port.icount.brk++;
380 if (uart_handle_break(&up->port))
384 up->port.icount.parity++;
386 up->port.icount.frame++;
388 up->port.icount.overrun++;
389 r1 &= up->port.read_status_mask;
397 if (uart_handle_sysrq_char(&up->port, ch))
400 if (up->port.ignore_status_mask == 0xff ||
401 (r1 & up->port.ignore_status_mask) == 0) {
411 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
424 if (ZS_IS_MOUSE(up))
425 sunzilog_kbdms_receive_chars(up, 0, 1);
426 if (ZS_IS_CONS(up)) {
441 if (ZS_WANTS_MODEM_STATUS(up)) {
443 up->port.icount.dsr++;
449 if ((status ^ up->prev_status) ^ DCD)
450 uart_handle_dcd_change(&up->port,
452 if ((status ^ up->prev_status) ^ CTS)
453 uart_handle_cts_change(&up->port,
456 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
459 up->prev_status = status;
462 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
467 if (ZS_IS_CONS(up)) {
483 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
485 if (ZS_REGS_HELD(up)) {
486 __load_zsregs(channel, up->curregs);
487 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
490 if (ZS_TX_STOPPED(up)) {
491 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
495 if (up->port.x_char) {
496 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
497 writeb(up->port.x_char, &channel->data);
501 up->port.icount.tx++;
502 up->port.x_char = 0;
506 if (up->port.state == NULL)
508 xmit = &up->port.state->xmit;
512 if (uart_tx_stopped(&up->port))
515 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
521 up->port.icount.tx++;
524 uart_write_wakeup(&up->port);
536 struct uart_sunzilog_port *up = dev_id;
538 while (up) {
540 = ZILOG_CHANNEL_FROM_PORT(&up->port);
544 spin_lock(&up->port.lock);
555 tty = sunzilog_receive_chars(up, channel);
557 sunzilog_status_handle(up, channel);
559 sunzilog_transmit_chars(up, channel);
561 spin_unlock(&up->port.lock);
567 up = up->next;
568 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
570 spin_lock(&up->port.lock);
578 tty = sunzilog_receive_chars(up, channel);
580 sunzilog_status_handle(up, channel);
582 sunzilog_transmit_chars(up, channel);
584 spin_unlock(&up->port.lock);
589 up = up->next;
653 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
669 up->curregs[R5] |= set_bits;
670 up->curregs[R5] &= ~clear_bits;
671 write_zsreg(channel, R5, up->curregs[R5]);
677 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
679 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
685 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
689 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
690 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
720 uart_write_wakeup(&up->port);
727 struct uart_sunzilog_port *up = UART_ZILOG(port);
730 if (ZS_IS_CONS(up))
736 up->curregs[R1] &= ~RxINT_MASK;
737 sunzilog_maybe_update_regs(up, channel);
743 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
747 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
748 if (new_reg != up->curregs[R15]) {
749 up->curregs[R15] = new_reg;
752 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
759 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
773 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
774 if (new_reg != up->curregs[R5]) {
775 up->curregs[R5] = new_reg;
778 write_zsreg(channel, R5, up->curregs[R5]);
784 static void __sunzilog_startup(struct uart_sunzilog_port *up)
788 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
789 up->prev_status = readb(&channel->control);
792 up->curregs[R3] |= RxENAB;
793 up->curregs[R5] |= TxENAB;
795 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
796 sunzilog_maybe_update_regs(up, channel);
801 struct uart_sunzilog_port *up = UART_ZILOG(port);
804 if (ZS_IS_CONS(up))
808 __sunzilog_startup(up);
840 struct uart_sunzilog_port *up = UART_ZILOG(port);
844 if (ZS_IS_CONS(up))
852 up->curregs[R3] &= ~RxENAB;
853 up->curregs[R5] &= ~TxENAB;
856 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
857 up->curregs[R5] &= ~SND_BRK;
858 sunzilog_maybe_update_regs(up, channel);
867 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
871 up->curregs[R10] = NRZ;
872 up->curregs[R11] = TCBR | RCBR;
875 up->curregs[R4] &= ~XCLK_MASK;
876 up->curregs[R4] |= X16CLK;
877 up->curregs[R12] = brg & 0xff;
878 up->curregs[R13] = (brg >> 8) & 0xff;
879 up->curregs[R14] = BRSRC | BRENAB;
882 up->curregs[R3] &= ~RxN_MASK;
883 up->curregs[R5] &= ~TxN_MASK;
886 up->curregs[R3] |= Rx5;
887 up->curregs[R5] |= Tx5;
888 up->parity_mask = 0x1f;
891 up->curregs[R3] |= Rx6;
892 up->curregs[R5] |= Tx6;
893 up->parity_mask = 0x3f;
896 up->curregs[R3] |= Rx7;
897 up->curregs[R5] |= Tx7;
898 up->parity_mask = 0x7f;
902 up->curregs[R3] |= Rx8;
903 up->curregs[R5] |= Tx8;
904 up->parity_mask = 0xff;
907 up->curregs[R4] &= ~0x0c;
909 up->curregs[R4] |= SB2;
911 up->curregs[R4] |= SB1;
913 up->curregs[R4] |= PAR_ENAB;
915 up->curregs[R4] &= ~PAR_ENAB;
917 up->curregs[R4] |= PAR_EVEN;
919 up->curregs[R4] &= ~PAR_EVEN;
921 up->port.read_status_mask = Rx_OVR;
923 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
925 up->port.read_status_mask |= BRK_ABRT;
927 up->port.ignore_status_mask = 0;
929 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
931 up->port.ignore_status_mask |= BRK_ABRT;
933 up->port.ignore_status_mask |= Rx_OVR;
937 up->port.ignore_status_mask = 0xff;
945 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
951 spin_lock_irqsave(&up->port.lock, flags);
955 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
957 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
958 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
960 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
962 up->cflag = termios->c_cflag;
964 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
968 spin_unlock_irqrestore(&up->port.lock, flags);
973 struct uart_sunzilog_port *up = UART_ZILOG(port);
975 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
1005 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
1007 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1032 ch &= up->parity_mask;
1039 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *)port;
1041 sunzilog_putchar(&up->port, ch);
1083 struct uart_sunzilog_port *up;
1094 up = &sunzilog_port_table[i];
1096 spin_lock_init(&up->port.lock);
1099 sunzilog_irq_chain = up;
1102 up->next = up + 1;
1104 up->next = NULL;
1155 struct uart_sunzilog_port *up = serio->port_data;
1160 sunzilog_putchar(&up->port, ch);
1169 struct uart_sunzilog_port *up = serio->port_data;
1174 if (!up->serio_open) {
1175 up->serio_open = 1;
1186 struct uart_sunzilog_port *up = serio->port_data;
1190 up->serio_open = 0;
1200 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1205 if (up->port.sysrq) {
1208 locked = spin_trylock(&up->port.lock);
1210 spin_lock(&up->port.lock);
1212 uart_console_write(&up->port, s, count, sunzilog_putchar);
1216 spin_unlock(&up->port.lock);
1222 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1226 if (up->port.type != PORT_SUNZILOG)
1233 sunserial_console_termios(con, up->port.dev->of_node);
1252 spin_lock_irqsave(&up->port.lock, flags);
1254 up->curregs[R15] |= BRKIE;
1255 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1257 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1258 __sunzilog_startup(up);
1260 spin_unlock_irqrestore(&up->port.lock, flags);
1284 static void __devinit sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1288 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1289 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1292 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1296 up->curregs[R15] |= BRKIE;
1298 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1299 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1300 __sunzilog_startup(up);
1304 static void __devinit sunzilog_register_serio(struct uart_sunzilog_port *up)
1306 struct serio *serio = &up->serio;
1308 serio->port_data = up;
1311 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1320 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1327 serio->dev.parent = up->port.dev;
1333 static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1339 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1341 spin_lock_irqsave(&up->port.lock, flags);
1342 if (ZS_IS_CHANNEL_A(up)) {
1348 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1350 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1351 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1352 up->curregs[R3] = RxENAB | Rx8;
1353 up->curregs[R5] = TxENAB | Tx8;
1354 up->curregs[R6] = 0x00; /* SDLC Address */
1355 up->curregs[R7] = 0x7E; /* SDLC Flag */
1356 up->curregs[R9] = NV;
1357 up->curregs[R7p] = 0x00;
1358 sunzilog_init_kbdms(up);
1360 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1361 up->curregs[R9] |= MIE;
1362 write_zsreg(channel, R9, up->curregs[R9]);
1365 up->parity_mask = 0xff;
1366 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1367 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1368 up->curregs[R3] = RxENAB | Rx8;
1369 up->curregs[R5] = TxENAB | Tx8;
1370 up->curregs[R6] = 0x00; /* SDLC Address */
1371 up->curregs[R7] = 0x7E; /* SDLC Flag */
1372 up->curregs[R9] = NV;
1373 up->curregs[R10] = NRZ;
1374 up->curregs[R11] = TCBR | RCBR;
1377 up->curregs[R12] = (brg & 0xff);
1378 up->curregs[R13] = (brg >> 8) & 0xff;
1379 up->curregs[R14] = BRSRC | BRENAB;
1380 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1381 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1382 if (__load_zsregs(channel, up->curregs)) {
1383 up->flags |= SUNZILOG_FLAG_ESCC;
1386 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1387 up->curregs[R9] |= MIE;
1388 write_zsreg(channel, R9, up->curregs[R9]);
1391 spin_unlock_irqrestore(&up->port.lock, flags);
1394 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1396 sunzilog_register_serio(up);
1406 struct uart_sunzilog_port *up;
1431 up = &sunzilog_port_table[inst * 2];
1434 up[0].port.mapbase = op->resource[0].start + 0x00;
1435 up[0].port.membase = (void __iomem *) &rp->channelA;
1436 up[0].port.iotype = UPIO_MEM;
1437 up[0].port.irq = op->archdata.irqs[0];
1438 up[0].port.uartclk = ZS_CLOCK;
1439 up[0].port.fifosize = 1;
1440 up[0].port.ops = &sunzilog_pops;
1441 up[0].port.type = PORT_SUNZILOG;
1442 up[0].port.flags = 0;
1443 up[0].port.line = (inst * 2) + 0;
1444 up[0].port.dev = &op->dev;
1445 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1447 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1448 sunzilog_init_hw(&up[0]);
1451 up[1].port.mapbase = op->resource[0].start + 0x04;
1452 up[1].port.membase = (void __iomem *) &rp->channelB;
1453 up[1].port.iotype = UPIO_MEM;
1454 up[1].port.irq = op->archdata.irqs[0];
1455 up[1].port.uartclk = ZS_CLOCK;
1456 up[1].port.fifosize = 1;
1457 up[1].port.ops = &sunzilog_pops;
1458 up[1].port.type = PORT_SUNZILOG;
1459 up[1].port.flags = 0;
1460 up[1].port.line = (inst * 2) + 1;
1461 up[1].port.dev = &op->dev;
1462 up[1].flags |= 0;
1464 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1465 sunzilog_init_hw(&up[1]);
1469 &sunzilog_reg, up[0].port.line,
1471 up->flags |= SUNZILOG_FLAG_IS_CONS;
1472 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1479 &sunzilog_reg, up[1].port.line,
1481 up->flags |= SUNZILOG_FLAG_IS_CONS;
1482 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1484 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1494 (unsigned long long) up[0].port.mapbase,
1495 op->archdata.irqs[0], sunzilog_type(&up[0].port));
1499 (unsigned long long) up[1].port.mapbase,
1500 op->archdata.irqs[0], sunzilog_type(&up[1].port));
1504 dev_set_drvdata(&op->dev, &up[0]);
1509 static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1511 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1513 serio_unregister_port(&up->serio);
1516 uart_remove_one_port(&sunzilog_reg, &up->port);
1521 struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
1524 zs_remove_one(&up[0]);
1525 zs_remove_one(&up[1]);
1527 regs = sunzilog_chip_regs[up[0].port.line / 2];
1584 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1591 while (up) {
1594 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1595 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1596 up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
1597 up->curregs[R9] |= MIE;
1598 write_zsreg(channel, R9, up->curregs[R9]);
1599 up = up->next;
1625 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1628 while (up) {
1631 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1632 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1633 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
1634 up->curregs[R9] &= ~MIE;
1635 write_zsreg(channel, R9, up->curregs[R9]);
1636 up = up->next;