Lines Matching refs:up
101 static unsigned int serial_in(struct uart_sunsu_port *up, int offset)
103 offset <<= up->port.regshift;
105 switch (up->port.iotype) {
107 outb(up->port.hub6 - 1 + offset, up->port.iobase);
108 return inb(up->port.iobase + 1);
111 return readb(up->port.membase + offset);
114 return inb(up->port.iobase + offset);
118 static void serial_out(struct uart_sunsu_port *up, int offset, int value)
132 offset <<= up->port.regshift;
134 switch (up->port.iotype) {
136 outb(up->port.hub6 - 1 + offset, up->port.iobase);
137 outb(value, up->port.iobase + 1);
141 writeb(value, up->port.membase + offset);
145 outb(value, up->port.iobase + offset);
155 #define serial_inp(up, offset) serial_in(up, offset)
156 #define serial_outp(up, offset, value) serial_out(up, offset, value)
162 static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
164 serial_out(up, UART_SCR, offset);
165 serial_out(up, UART_ICR, value);
174 static int __enable_rsa(struct uart_sunsu_port *up)
179 mode = serial_inp(up, UART_RSA_MSR);
183 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
184 mode = serial_inp(up, UART_RSA_MSR);
189 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
194 static void enable_rsa(struct uart_sunsu_port *up)
196 if (up->port.type == PORT_RSA) {
197 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
198 spin_lock_irq(&up->port.lock);
199 __enable_rsa(up);
200 spin_unlock_irq(&up->port.lock);
202 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
203 serial_outp(up, UART_RSA_FRR, 0);
213 static void disable_rsa(struct uart_sunsu_port *up)
218 if (up->port.type == PORT_RSA &&
219 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
220 spin_lock_irq(&up->port.lock);
222 mode = serial_inp(up, UART_RSA_MSR);
226 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
227 mode = serial_inp(up, UART_RSA_MSR);
232 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
233 spin_unlock_irq(&up->port.lock);
248 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
250 __stop_tx(up);
255 if (up->port.type == PORT_16C950) {
256 up->acr |= UART_ACR_TXDIS;
257 serial_icr_write(up, UART_ACR, up->acr);
263 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
265 if (!(up->ier & UART_IER_THRI)) {
266 up->ier |= UART_IER_THRI;
267 serial_out(up, UART_IER, up->ier);
273 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
274 up->acr &= ~UART_ACR_TXDIS;
275 serial_icr_write(up, UART_ACR, up->acr);
281 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
283 up->ier &= ~UART_IER_RLSI;
284 up->port.read_status_mask &= ~UART_LSR_DR;
285 serial_out(up, UART_IER, up->ier);
290 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
293 spin_lock_irqsave(&up->port.lock, flags);
294 up->ier |= UART_IER_MSI;
295 serial_out(up, UART_IER, up->ier);
296 spin_unlock_irqrestore(&up->port.lock, flags);
300 receive_chars(struct uart_sunsu_port *up, unsigned char *status)
302 struct tty_struct *tty = up->port.state->port.tty;
308 ch = serial_inp(up, UART_RX);
310 up->port.icount.rx++;
319 up->port.icount.brk++;
320 if (up->port.cons != NULL &&
321 up->port.line == up->port.cons->index)
329 if (uart_handle_break(&up->port))
332 up->port.icount.parity++;
334 up->port.icount.frame++;
336 up->port.icount.overrun++;
341 *status &= up->port.read_status_mask;
343 if (up->port.cons != NULL &&
344 up->port.line == up->port.cons->index) {
346 *status |= up->lsr_break_flag;
347 up->lsr_break_flag = 0;
357 if (uart_handle_sysrq_char(&up->port, ch))
359 if ((*status & up->port.ignore_status_mask) == 0)
369 *status = serial_inp(up, UART_LSR);
378 static void transmit_chars(struct uart_sunsu_port *up)
380 struct circ_buf *xmit = &up->port.state->xmit;
383 if (up->port.x_char) {
384 serial_outp(up, UART_TX, up->port.x_char);
385 up->port.icount.tx++;
386 up->port.x_char = 0;
389 if (uart_tx_stopped(&up->port)) {
390 sunsu_stop_tx(&up->port);
394 __stop_tx(up);
398 count = up->port.fifosize;
400 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
402 up->port.icount.tx++;
408 uart_write_wakeup(&up->port);
411 __stop_tx(up);
414 static void check_modem_status(struct uart_sunsu_port *up)
418 status = serial_in(up, UART_MSR);
424 up->port.icount.rng++;
426 up->port.icount.dsr++;
428 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
430 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
432 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
437 struct uart_sunsu_port *up = dev_id;
441 spin_lock_irqsave(&up->port.lock, flags);
446 status = serial_inp(up, UART_LSR);
449 tty = receive_chars(up, &status);
450 check_modem_status(up);
452 transmit_chars(up);
454 spin_unlock_irqrestore(&up->port.lock, flags);
459 spin_lock_irqsave(&up->port.lock, flags);
461 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
463 spin_unlock_irqrestore(&up->port.lock, flags);
474 static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
476 unsigned int cur_cflag = up->cflag;
479 up->cflag &= ~CBAUD;
480 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
482 quot = up->port.uartclk / (16 * new_baud);
484 sunsu_change_speed(&up->port, up->cflag, 0, quot);
487 static void receive_kbd_ms_chars(struct uart_sunsu_port *up, int is_break)
490 unsigned char ch = serial_inp(up, UART_RX);
493 if (up->su_type == SU_PORT_KBD) {
495 serio_interrupt(&up->serio, ch, 0);
497 } else if (up->su_type == SU_PORT_MS) {
502 sunsu_change_mouse_baud(up);
509 serio_interrupt(&up->serio, ch, 0);
514 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
519 struct uart_sunsu_port *up = dev_id;
521 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
522 unsigned char status = serial_inp(up, UART_LSR);
525 receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0);
533 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
537 spin_lock_irqsave(&up->port.lock, flags);
538 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
539 spin_unlock_irqrestore(&up->port.lock, flags);
546 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
550 status = serial_in(up, UART_MSR);
566 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
580 serial_out(up, UART_MCR, mcr);
585 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
588 spin_lock_irqsave(&up->port.lock, flags);
590 up->lcr |= UART_LCR_SBC;
592 up->lcr &= ~UART_LCR_SBC;
593 serial_out(up, UART_LCR, up->lcr);
594 spin_unlock_irqrestore(&up->port.lock, flags);
599 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
603 if (up->port.type == PORT_16C950) {
604 /* Wake up and initialize UART */
605 up->acr = 0;
606 serial_outp(up, UART_LCR, 0xBF);
607 serial_outp(up, UART_EFR, UART_EFR_ECB);
608 serial_outp(up, UART_IER, 0);
609 serial_outp(up, UART_LCR, 0);
610 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
611 serial_outp(up, UART_LCR, 0xBF);
612 serial_outp(up, UART_EFR, UART_EFR_ECB);
613 serial_outp(up, UART_LCR, 0);
618 * If this is an RSA port, see if we can kick it up to the
621 enable_rsa(up);
628 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
629 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
630 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
632 serial_outp(up, UART_FCR, 0);
638 (void) serial_inp(up, UART_LSR);
639 (void) serial_inp(up, UART_RX);
640 (void) serial_inp(up, UART_IIR);
641 (void) serial_inp(up, UART_MSR);
648 if (!(up->port.flags & UPF_BUGGY_UART) &&
649 (serial_inp(up, UART_LSR) == 0xff)) {
650 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
654 if (up->su_type != SU_PORT_PORT) {
655 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
656 IRQF_SHARED, su_typev[up->su_type], up);
658 retval = request_irq(up->port.irq, sunsu_serial_interrupt,
659 IRQF_SHARED, su_typev[up->su_type], up);
662 printk("su: Cannot register IRQ %d\n", up->port.irq);
669 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
671 spin_lock_irqsave(&up->port.lock, flags);
673 up->port.mctrl |= TIOCM_OUT2;
675 sunsu_set_mctrl(&up->port, up->port.mctrl);
676 spin_unlock_irqrestore(&up->port.lock, flags);
683 up->ier = UART_IER_RLSI | UART_IER_RDI;
684 serial_outp(up, UART_IER, up->ier);
686 if (up->port.flags & UPF_FOURPORT) {
691 icp = (up->port.iobase & 0xfe0) | 0x01f;
699 (void) serial_inp(up, UART_LSR);
700 (void) serial_inp(up, UART_RX);
701 (void) serial_inp(up, UART_IIR);
702 (void) serial_inp(up, UART_MSR);
709 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
715 up->ier = 0;
716 serial_outp(up, UART_IER, 0);
718 spin_lock_irqsave(&up->port.lock, flags);
719 if (up->port.flags & UPF_FOURPORT) {
721 inb((up->port.iobase & 0xfe0) | 0x1f);
722 up->port.mctrl |= TIOCM_OUT1;
724 up->port.mctrl &= ~TIOCM_OUT2;
726 sunsu_set_mctrl(&up->port, up->port.mctrl);
727 spin_unlock_irqrestore(&up->port.lock, flags);
732 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
733 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
736 serial_outp(up, UART_FCR, 0);
742 disable_rsa(up);
748 (void) serial_in(up, UART_RX);
750 free_irq(up->port.irq, up);
757 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
788 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
789 up->rev == 0x5201)
792 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
793 if ((up->port.uartclk / quot) < (2400 * 16))
796 else if (up->port.type == PORT_RSA)
802 if (up->port.type == PORT_16750)
809 spin_lock_irqsave(&up->port.lock, flags);
816 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
818 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
820 up->port.read_status_mask |= UART_LSR_BI;
825 up->port.ignore_status_mask = 0;
827 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
829 up->port.ignore_status_mask |= UART_LSR_BI;
835 up->port.ignore_status_mask |= UART_LSR_OE;
842 up->port.ignore_status_mask |= UART_LSR_DR;
847 up->ier &= ~UART_IER_MSI;
848 if (UART_ENABLE_MS(&up->port, cflag))
849 up->ier |= UART_IER_MSI;
851 serial_out(up, UART_IER, up->ier);
853 if (uart_config[up->port.type].flags & UART_STARTECH) {
854 serial_outp(up, UART_LCR, 0xBF);
855 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
857 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
858 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
859 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
860 if (up->port.type == PORT_16750)
861 serial_outp(up, UART_FCR, fcr); /* set fcr */
862 serial_outp(up, UART_LCR, cval); /* reset DLAB */
863 up->lcr = cval; /* Save LCR */
864 if (up->port.type != PORT_16750) {
867 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
869 serial_outp(up, UART_FCR, fcr); /* set fcr */
872 up->cflag = cflag;
874 spin_unlock_irqrestore(&up->port.lock, flags);
903 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
911 port->type = up->type_probed;
960 struct uart_sunsu_port *up = serio->port_data;
967 lsr = serial_in(up, UART_LSR);
971 serial_out(up, UART_TX, ch);
980 struct uart_sunsu_port *up = serio->port_data;
985 if (!up->serio_open) {
986 up->serio_open = 1;
997 struct uart_sunsu_port *up = serio->port_data;
1001 up->serio_open = 0;
1007 static void sunsu_autoconfig(struct uart_sunsu_port *up)
1013 if (up->su_type == SU_PORT_NONE)
1016 up->type_probed = PORT_UNKNOWN;
1017 up->port.iotype = UPIO_MEM;
1019 spin_lock_irqsave(&up->port.lock, flags);
1021 if (!(up->port.flags & UPF_BUGGY_UART)) {
1031 scratch = serial_inp(up, UART_IER);
1032 serial_outp(up, UART_IER, 0);
1036 scratch2 = serial_inp(up, UART_IER);
1037 serial_outp(up, UART_IER, 0x0f);
1041 scratch3 = serial_inp(up, UART_IER);
1042 serial_outp(up, UART_IER, scratch);
1047 save_mcr = serial_in(up, UART_MCR);
1048 save_lcr = serial_in(up, UART_LCR);
1059 if (!(up->port.flags & UPF_SKIP_TEST)) {
1060 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1061 status1 = serial_inp(up, UART_MSR) & 0xF0;
1062 serial_outp(up, UART_MCR, save_mcr);
1066 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */
1067 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */
1068 serial_outp(up, UART_LCR, 0);
1069 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1070 scratch = serial_in(up, UART_IIR) >> 6;
1073 up->port.type = PORT_16450;
1076 up->port.type = PORT_UNKNOWN;
1079 up->port.type = PORT_16550;
1082 up->port.type = PORT_16550A;
1085 if (up->port.type == PORT_16550A) {
1087 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1088 if (serial_in(up, UART_EFR) == 0) {
1089 up->port.type = PORT_16650;
1091 serial_outp(up, UART_LCR, 0xBF);
1092 if (serial_in(up, UART_EFR) == 0)
1093 up->port.type = PORT_16650V2;
1096 if (up->port.type == PORT_16550A) {
1098 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB);
1099 serial_outp(up, UART_FCR,
1101 scratch = serial_in(up, UART_IIR) >> 5;
1109 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1110 serial_outp(up, UART_LCR, 0);
1111 serial_outp(up, UART_FCR,
1113 scratch = serial_in(up, UART_IIR) >> 5;
1115 up->port.type = PORT_16750;
1117 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1119 serial_outp(up, UART_LCR, save_lcr);
1120 if (up->port.type == PORT_16450) {
1121 scratch = serial_in(up, UART_SCR);
1122 serial_outp(up, UART_SCR, 0xa5);
1123 status1 = serial_in(up, UART_SCR);
1124 serial_outp(up, UART_SCR, 0x5a);
1125 status2 = serial_in(up, UART_SCR);
1126 serial_outp(up, UART_SCR, scratch);
1129 up->port.type = PORT_8250;
1132 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
1134 if (up->port.type == PORT_UNKNOWN)
1136 up->type_probed = up->port.type;
1142 if (up->port.type == PORT_RSA)
1143 serial_outp(up, UART_RSA_FRR, 0);
1145 serial_outp(up, UART_MCR, save_mcr);
1146 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
1149 serial_outp(up, UART_FCR, 0);
1150 (void)serial_in(up, UART_RX);
1151 serial_outp(up, UART_IER, 0);
1154 spin_unlock_irqrestore(&up->port.lock, flags);
1164 static int __devinit sunsu_kbd_ms_init(struct uart_sunsu_port *up)
1171 if (up->su_type == SU_PORT_KBD) {
1172 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1175 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1178 quot = up->port.uartclk / (16 * baud);
1180 sunsu_autoconfig(up);
1181 if (up->port.type == PORT_UNKNOWN)
1185 up->port.dev->of_node->full_name,
1186 (up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse",
1187 (unsigned long long) up->port.mapbase,
1188 up->port.irq);
1191 serio = &up->serio;
1192 serio->port_data = up;
1195 if (up->su_type == SU_PORT_KBD) {
1204 (!(up->port.line & 1) ? "su/serio0" : "su/serio1"),
1210 serio->dev.parent = up->port.dev;
1215 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1217 sunsu_startup(&up->port);
1234 static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up)
1238 /* Wait up to 10ms for the character(s) to be sent. */
1240 status = serial_in(up, UART_LSR);
1243 up->lsr_break_flag = UART_LSR_BI;
1250 /* Wait up to 1s for flow control if necessary */
1251 if (up->port.flags & UPF_CONS_FLOW) {
1254 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1261 struct uart_sunsu_port *up = (struct uart_sunsu_port *)port;
1263 wait_for_xmitr(up);
1264 serial_out(up, UART_TX, ch);
1274 struct uart_sunsu_port *up = &sunsu_ports[co->index];
1280 if (up->port.sysrq) {
1283 locked = spin_trylock(&up->port.lock);
1285 spin_lock(&up->port.lock);
1290 ier = serial_in(up, UART_IER);
1291 serial_out(up, UART_IER, 0);
1293 uart_console_write(&up->port, s, count, sunsu_console_putchar);
1299 wait_for_xmitr(up);
1300 serial_out(up, UART_IER, ier);
1303 spin_unlock(&up->port.lock);
1395 struct uart_sunsu_port *up;
1405 up = &sunsu_ports[inst];
1407 up = kzalloc(sizeof(*up), GFP_KERNEL);
1408 if (!up)
1412 up->port.line = inst;
1414 spin_lock_init(&up->port.lock);
1416 up->su_type = type;
1419 up->port.mapbase = rp->start;
1420 up->reg_size = (rp->end - rp->start) + 1;
1421 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su");
1422 if (!up->port.membase) {
1424 kfree(up);
1428 up->port.irq = op->archdata.irqs[0];
1430 up->port.dev = &op->dev;
1432 up->port.type = PORT_UNKNOWN;
1433 up->port.uartclk = (SU_BASE_BAUD * 16);
1436 if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) {
1437 err = sunsu_kbd_ms_init(up);
1440 up->port.membase, up->reg_size);
1441 kfree(up);
1444 dev_set_drvdata(&op->dev, up);
1449 up->port.flags |= UPF_BOOT_AUTOCONF;
1451 sunsu_autoconfig(up);
1454 if (up->port.type == PORT_UNKNOWN)
1457 up->port.ops = &sunsu_pops;
1465 &sunsu_reg, up->port.line,
1467 err = uart_add_one_port(&sunsu_reg, &up->port);
1471 dev_set_drvdata(&op->dev, up);
1478 of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
1484 struct uart_sunsu_port *up = dev_get_drvdata(&op->dev);
1487 if (up->su_type == SU_PORT_MS ||
1488 up->su_type == SU_PORT_KBD)
1493 serio_unregister_port(&up->serio);
1495 } else if (up->port.type != PORT_UNKNOWN)
1496 uart_remove_one_port(&sunsu_reg, &up->port);
1498 if (up->port.membase)
1499 of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
1502 kfree(up);