Lines Matching refs:up
41 static void wait_for_bits(struct nwpserial_port *up, int bits)
45 /* Wait up to 10ms for the character(s) to be sent. */
47 status = dcr_read(up->dcr_host, UART_LSR);
58 struct nwpserial_port *up;
59 up = container_of(port, struct nwpserial_port, port);
61 wait_for_bits(up, UART_LSR_THRE);
62 dcr_write(up->dcr_host, UART_TX, c);
63 up->port.icount.tx++;
69 struct nwpserial_port *up = &nwpserial_ports[co->index];
74 locked = spin_trylock_irqsave(&up->port.lock, flags);
76 spin_lock_irqsave(&up->port.lock, flags);
79 up->ier = dcr_read(up->dcr_host, UART_IER);
80 dcr_write(up->dcr_host, UART_IER, up->ier & ~UART_IER_RDI);
82 uart_console_write(&up->port, s, count, nwpserial_console_putchar);
85 while ((dcr_read(up->dcr_host, UART_LSR) & UART_LSR_THRE) == 0)
89 dcr_write(up->dcr_host, UART_IER, up->ier);
92 spin_unlock_irqrestore(&up->port.lock, flags);
128 struct nwpserial_port *up = dev_id;
129 struct tty_struct *tty = up->port.state->port.tty;
134 spin_lock(&up->port.lock);
137 iir = dcr_read(up->dcr_host, UART_IIR);
144 up->port.icount.rx++;
145 ch = dcr_read(up->dcr_host, UART_RX);
146 if (up->port.ignore_status_mask != NWPSERIAL_STATUS_RXVALID)
148 } while (dcr_read(up->dcr_host, UART_LSR) & UART_LSR_DR);
154 dcr_write(up->dcr_host, UART_IIR, 1);
156 spin_unlock(&up->port.lock);
162 struct nwpserial_port *up;
165 up = container_of(port, struct nwpserial_port, port);
168 up->mcr = dcr_read(up->dcr_host, UART_MCR) & ~UART_MCR_AFE;
169 dcr_write(up->dcr_host, UART_MCR, up->mcr);
172 err = request_irq(up->port.irq, nwpserial_interrupt,
173 IRQF_SHARED, "nwpserial", up);
178 up->ier = UART_IER_RDI;
179 dcr_write(up->dcr_host, UART_IER, up->ier);
182 up->port.ignore_status_mask &= ~NWPSERIAL_STATUS_RXVALID;
189 struct nwpserial_port *up;
190 up = container_of(port, struct nwpserial_port, port);
193 up->port.ignore_status_mask |= NWPSERIAL_STATUS_RXVALID;
196 up->ier = 0;
197 dcr_write(up->dcr_host, UART_IER, up->ier);
200 free_irq(up->port.irq, port);
217 struct nwpserial_port *up;
218 up = container_of(port, struct nwpserial_port, port);
220 up->port.read_status_mask = NWPSERIAL_STATUS_RXVALID
223 up->port.ignore_status_mask = 0;
226 up->port.ignore_status_mask |= NWPSERIAL_STATUS_RXVALID;
245 struct nwpserial_port *up;
246 up = container_of(port, struct nwpserial_port, port);
248 up->port.ignore_status_mask = NWPSERIAL_STATUS_RXVALID;
251 static void nwpserial_putchar(struct nwpserial_port *up, unsigned char c)
254 wait_for_bits(up, UART_LSR_THRE);
255 dcr_write(up->dcr_host, UART_TX, c);
256 up->port.icount.tx++;
261 struct nwpserial_port *up;
263 up = container_of(port, struct nwpserial_port, port);
264 xmit = &up->port.state->xmit;
267 nwpserial_putchar(up, up->port.x_char);
271 while (!(uart_circ_empty(xmit) || uart_tx_stopped(&up->port))) {
272 nwpserial_putchar(up, xmit->buf[xmit->tail]);
294 struct nwpserial_port *up;
297 up = container_of(port, struct nwpserial_port, port);
299 spin_lock_irqsave(&up->port.lock, flags);
300 ret = dcr_read(up->dcr_host, UART_LSR);
301 spin_unlock_irqrestore(&up->port.lock, flags);
337 struct nwpserial_port *up = NULL;
357 up = &nwpserial_ports[i];
362 if (up == NULL)
366 up = &nwpserial_ports[i];
370 if (up == NULL) {
379 up->port.membase = port->membase;
380 up->port.irq = port->irq;
381 up->port.uartclk = port->uartclk;
382 up->port.fifosize = port->fifosize;
383 up->port.regshift = port->regshift;
384 up->port.iotype = port->iotype;
385 up->port.flags = port->flags;
386 up->port.mapbase = port->mapbase;
387 up->port.private_data = port->private_data;
390 up->port.dev = port->dev;
392 if (up->port.iobase != dcr_base) {
393 up->port.ops = &nwpserial_pops;
394 up->port.fifosize = 16;
396 spin_lock_init(&up->port.lock);
398 up->port.iobase = dcr_base;
401 up->dcr_host = dcr_map(dn, dcr_base, dcr_len);
402 if (!DCR_MAP_OK(up->dcr_host)) {
408 ret = uart_add_one_port(&nwpserial_reg, &up->port);
410 ret = up->port.line;
421 struct nwpserial_port *up = &nwpserial_ports[line];
423 uart_remove_one_port(&nwpserial_reg, &up->port);
425 up->port.type = PORT_UNKNOWN;
434 struct nwpserial_port *up = NULL;
444 up = &nwpserial_ports[i];
448 if (up == NULL)
459 spin_lock_init(&up->port.lock);
460 up->port.ops = &nwpserial_pops;
461 up->port.type = PORT_NWPSERIAL;
462 up->port.fifosize = 16;
466 up->port.iobase = dcr_base;
468 up->dcr_host = dcr_map(dn, dcr_base, dcr_len);
469 if (!DCR_MAP_OK(up->dcr_host)) {