Lines Matching refs:up
382 #define map_8250_in_reg(up, offset) (offset)
383 #define map_8250_out_reg(up, offset) (offset)
462 struct uart_8250_port *up = (struct uart_8250_port *)p;
463 up->lcr = value;
486 struct uart_8250_port *up = (struct uart_8250_port *)p;
525 up->cur_iotype = p->iotype;
529 serial_out_sync(struct uart_8250_port *up, int offset, int value)
531 struct uart_port *p = &up->port;
545 #define serial_in(up, offset) \
546 (up->port.serial_in(&(up)->port, (offset)))
547 #define serial_out(up, offset, value) \
548 (up->port.serial_out(&(up)->port, (offset), (value)))
555 #define serial_inp(up, offset) serial_in(up, offset)
556 #define serial_outp(up, offset, value) serial_out(up, offset, value)
559 static inline int _serial_dl_read(struct uart_8250_port *up)
561 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
565 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
567 serial_outp(up, UART_DLL, value & 0xff);
568 serial_outp(up, UART_DLM, value >> 8 & 0xff);
573 static int serial_dl_read(struct uart_8250_port *up)
575 if (up->port.iotype == UPIO_AU)
576 return __raw_readl(up->port.membase + 0x28);
578 return _serial_dl_read(up);
581 static void serial_dl_write(struct uart_8250_port *up, int value)
583 if (up->port.iotype == UPIO_AU)
584 __raw_writel(value, up->port.membase + 0x28);
586 _serial_dl_write(up, value);
589 static int serial_dl_read(struct uart_8250_port *up)
591 return (up->port.iotype == UPIO_RM9000) ?
592 (((__raw_readl(up->port.membase + 0x10) << 8) |
593 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
594 _serial_dl_read(up);
597 static void serial_dl_write(struct uart_8250_port *up, int value)
599 if (up->port.iotype == UPIO_RM9000) {
600 __raw_writel(value, up->port.membase + 0x08);
601 __raw_writel(value >> 8, up->port.membase + 0x10);
603 _serial_dl_write(up, value);
607 #define serial_dl_read(up) _serial_dl_read(up)
608 #define serial_dl_write(up, value) _serial_dl_write(up, value)
614 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
616 serial_out(up, UART_SCR, offset);
617 serial_out(up, UART_ICR, value);
620 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
624 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
625 serial_out(up, UART_SCR, offset);
626 value = serial_in(up, UART_ICR);
627 serial_icr_write(up, UART_ACR, up->acr);
672 static int __enable_rsa(struct uart_8250_port *up)
677 mode = serial_inp(up, UART_RSA_MSR);
681 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
682 mode = serial_inp(up, UART_RSA_MSR);
687 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
692 static void enable_rsa(struct uart_8250_port *up)
694 if (up->port.type == PORT_RSA) {
695 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
696 spin_lock_irq(&up->port.lock);
697 __enable_rsa(up);
698 spin_unlock_irq(&up->port.lock);
700 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
701 serial_outp(up, UART_RSA_FRR, 0);
711 static void disable_rsa(struct uart_8250_port *up)
716 if (up->port.type == PORT_RSA &&
717 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
718 spin_lock_irq(&up->port.lock);
720 mode = serial_inp(up, UART_RSA_MSR);
724 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
725 mode = serial_inp(up, UART_RSA_MSR);
730 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
731 spin_unlock_irq(&up->port.lock);
740 static int size_fifo(struct uart_8250_port *up)
746 old_lcr = serial_inp(up, UART_LCR);
747 serial_outp(up, UART_LCR, 0);
748 old_fcr = serial_inp(up, UART_FCR);
749 old_mcr = serial_inp(up, UART_MCR);
750 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
752 serial_outp(up, UART_MCR, UART_MCR_LOOP);
753 serial_outp(up, UART_LCR, UART_LCR_DLAB);
754 old_dl = serial_dl_read(up);
755 serial_dl_write(up, 0x0001);
756 serial_outp(up, UART_LCR, 0x03);
758 serial_outp(up, UART_TX, count);
760 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
762 serial_inp(up, UART_RX);
763 serial_outp(up, UART_FCR, old_fcr);
764 serial_outp(up, UART_MCR, old_mcr);
765 serial_outp(up, UART_LCR, UART_LCR_DLAB);
766 serial_dl_write(up, old_dl);
767 serial_outp(up, UART_LCR, old_lcr);
810 static void autoconfig_has_efr(struct uart_8250_port *up)
817 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
823 * Semiconductor clone chips lock up if you try writing to the
836 up->acr = 0;
837 serial_out(up, UART_LCR, 0xBF);
838 serial_out(up, UART_EFR, UART_EFR_ECB);
839 serial_out(up, UART_LCR, 0x00);
840 id1 = serial_icr_read(up, UART_ID1);
841 id2 = serial_icr_read(up, UART_ID2);
842 id3 = serial_icr_read(up, UART_ID3);
843 rev = serial_icr_read(up, UART_REV);
849 up->port.type = PORT_16C950;
852 up->bugs |= UART_BUG_QUOT;
864 id1 = autoconfig_read_divisor_id(up);
869 up->port.type = PORT_16850;
882 if (size_fifo(up) == 64)
883 up->port.type = PORT_16654;
885 up->port.type = PORT_16650V2;
893 static void autoconfig_8250(struct uart_8250_port *up)
897 up->port.type = PORT_8250;
899 scratch = serial_in(up, UART_SCR);
900 serial_outp(up, UART_SCR, 0xa5);
901 status1 = serial_in(up, UART_SCR);
902 serial_outp(up, UART_SCR, 0x5a);
903 status2 = serial_in(up, UART_SCR);
904 serial_outp(up, UART_SCR, scratch);
907 up->port.type = PORT_16450;
910 static int broken_efr(struct uart_8250_port *up)
917 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
929 static void autoconfig_16550a(struct uart_8250_port *up)
934 up->port.type = PORT_16550A;
935 up->capabilities |= UART_CAP_FIFO;
941 serial_outp(up, UART_LCR, UART_LCR_DLAB);
942 if (serial_in(up, UART_EFR) == 0) {
943 serial_outp(up, UART_EFR, 0xA8);
944 if (serial_in(up, UART_EFR) != 0) {
946 up->port.type = PORT_16650;
947 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
951 serial_outp(up, UART_EFR, 0);
959 serial_outp(up, UART_LCR, 0xBF);
960 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
962 autoconfig_has_efr(up);
973 serial_outp(up, UART_LCR, 0);
974 status1 = serial_in(up, UART_MCR);
975 serial_outp(up, UART_LCR, 0xE0);
976 status2 = serial_in(up, 0x02); /* EXCR1 */
979 serial_outp(up, UART_LCR, 0);
980 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
981 serial_outp(up, UART_LCR, 0xE0);
982 status2 = serial_in(up, 0x02); /* EXCR1 */
983 serial_outp(up, UART_LCR, 0);
984 serial_outp(up, UART_MCR, status1);
989 serial_outp(up, UART_LCR, 0xE0);
991 quot = serial_dl_read(up);
994 status1 = serial_in(up, 0x04); /* EXCR2 */
997 serial_outp(up, 0x04, status1);
999 serial_dl_write(up, quot);
1001 serial_outp(up, UART_LCR, 0);
1003 up->port.uartclk = 921600*16;
1004 up->port.type = PORT_NS16550A;
1005 up->capabilities |= UART_NATSEMI;
1016 serial_outp(up, UART_LCR, 0);
1017 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1018 status1 = serial_in(up, UART_IIR) >> 5;
1019 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1020 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1021 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1022 status2 = serial_in(up, UART_IIR) >> 5;
1023 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1024 serial_outp(up, UART_LCR, 0);
1029 up->port.type = PORT_16750;
1030 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1042 iersave = serial_in(up, UART_IER);
1043 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1044 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1049 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1050 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1056 up->port.type = PORT_XSCALE;
1057 up->capabilities |= UART_CAP_UUE;
1067 serial_outp(up, UART_IER, iersave);
1073 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1074 up->port.type = PORT_U6_16550A;
1075 up->capabilities |= UART_CAP_AFE;
1086 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1092 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1096 serial_index(&up->port), up->port.iobase, up->port.membase);
1102 spin_lock_irqsave(&up->port.lock, flags);
1104 up->capabilities = 0;
1105 up->bugs = 0;
1107 if (!(up->port.flags & UPF_BUGGY_UART)) {
1121 scratch = serial_inp(up, UART_IER);
1122 serial_outp(up, UART_IER, 0);
1130 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1131 serial_outp(up, UART_IER, 0x0F);
1135 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1136 serial_outp(up, UART_IER, scratch);
1147 save_mcr = serial_in(up, UART_MCR);
1148 save_lcr = serial_in(up, UART_LCR);
1159 if (!(up->port.flags & UPF_SKIP_TEST)) {
1160 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1161 status1 = serial_inp(up, UART_MSR) & 0xF0;
1162 serial_outp(up, UART_MCR, save_mcr);
1179 serial_outp(up, UART_LCR, 0xBF);
1180 serial_outp(up, UART_EFR, 0);
1181 serial_outp(up, UART_LCR, 0);
1183 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1184 scratch = serial_in(up, UART_IIR) >> 6;
1190 autoconfig_8250(up);
1193 up->port.type = PORT_UNKNOWN;
1196 up->port.type = PORT_16550;
1199 autoconfig_16550a(up);
1207 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1211 if (probe_rsa[i] == up->port.iobase &&
1212 __enable_rsa(up)) {
1213 up->port.type = PORT_RSA;
1220 serial_outp(up, UART_LCR, save_lcr);
1222 if (up->capabilities != uart_config[up->port.type].flags) {
1225 serial_index(&up->port), up->capabilities,
1226 uart_config[up->port.type].flags);
1229 up->port.fifosize = uart_config[up->port.type].fifo_size;
1230 up->capabilities = uart_config[up->port.type].flags;
1231 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1233 if (up->port.type == PORT_UNKNOWN)
1240 if (up->port.type == PORT_RSA)
1241 serial_outp(up, UART_RSA_FRR, 0);
1243 serial_outp(up, UART_MCR, save_mcr);
1244 serial8250_clear_fifos(up);
1245 serial_in(up, UART_RX);
1246 if (up->capabilities & UART_CAP_UUE)
1247 serial_outp(up, UART_IER, UART_IER_UUE);
1249 serial_outp(up, UART_IER, 0);
1252 spin_unlock_irqrestore(&up->port.lock, flags);
1253 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1256 static void autoconfig_irq(struct uart_8250_port *up)
1264 if (up->port.flags & UPF_FOURPORT) {
1265 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1273 save_mcr = serial_inp(up, UART_MCR);
1274 save_ier = serial_inp(up, UART_IER);
1275 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1278 serial_outp(up, UART_MCR, 0);
1280 if (up->port.flags & UPF_FOURPORT) {
1281 serial_outp(up, UART_MCR,
1284 serial_outp(up, UART_MCR,
1287 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1288 (void)serial_inp(up, UART_LSR);
1289 (void)serial_inp(up, UART_RX);
1290 (void)serial_inp(up, UART_IIR);
1291 (void)serial_inp(up, UART_MSR);
1292 serial_outp(up, UART_TX, 0xFF);
1296 serial_outp(up, UART_MCR, save_mcr);
1297 serial_outp(up, UART_IER, save_ier);
1299 if (up->port.flags & UPF_FOURPORT)
1302 up->port.irq = (irq > 0) ? irq : 0;
1315 struct uart_8250_port *up = (struct uart_8250_port *)port;
1317 __stop_tx(up);
1322 if (up->port.type == PORT_16C950) {
1323 up->acr |= UART_ACR_TXDIS;
1324 serial_icr_write(up, UART_ACR, up->acr);
1328 static void transmit_chars(struct uart_8250_port *up);
1332 struct uart_8250_port *up = (struct uart_8250_port *)port;
1334 if (!(up->ier & UART_IER_THRI)) {
1335 up->ier |= UART_IER_THRI;
1336 serial_out(up, UART_IER, up->ier);
1338 if (up->bugs & UART_BUG_TXEN) {
1340 lsr = serial_in(up, UART_LSR);
1341 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1342 if ((up->port.type == PORT_RM9000) ?
1345 transmit_chars(up);
1352 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1353 up->acr &= ~UART_ACR_TXDIS;
1354 serial_icr_write(up, UART_ACR, up->acr);
1360 struct uart_8250_port *up = (struct uart_8250_port *)port;
1362 up->ier &= ~UART_IER_RLSI;
1363 up->port.read_status_mask &= ~UART_LSR_DR;
1364 serial_out(up, UART_IER, up->ier);
1369 struct uart_8250_port *up = (struct uart_8250_port *)port;
1372 if (up->bugs & UART_BUG_NOMSR)
1375 up->ier |= UART_IER_MSI;
1376 serial_out(up, UART_IER, up->ier);
1380 receive_chars(struct uart_8250_port *up, unsigned int *status)
1382 struct tty_struct *tty = up->port.state->port.tty;
1389 ch = serial_inp(up, UART_RX);
1401 up->port.icount.rx++;
1403 lsr |= up->lsr_saved_flags;
1404 up->lsr_saved_flags = 0;
1412 up->port.icount.brk++;
1419 if (uart_handle_break(&up->port))
1422 up->port.icount.parity++;
1424 up->port.icount.frame++;
1426 up->port.icount.overrun++;
1431 lsr &= up->port.read_status_mask;
1441 if (uart_handle_sysrq_char(&up->port, ch))
1444 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1447 lsr = serial_inp(up, UART_LSR);
1449 spin_unlock(&up->port.lock);
1451 spin_lock(&up->port.lock);
1455 static void transmit_chars(struct uart_8250_port *up)
1457 struct circ_buf *xmit = &up->port.state->xmit;
1460 if (up->port.x_char) {
1461 serial_outp(up, UART_TX, up->port.x_char);
1462 up->port.icount.tx++;
1463 up->port.x_char = 0;
1466 if (uart_tx_stopped(&up->port)) {
1467 serial8250_stop_tx(&up->port);
1471 __stop_tx(up);
1475 count = up->tx_loadsz;
1477 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1479 up->port.icount.tx++;
1485 uart_write_wakeup(&up->port);
1490 __stop_tx(up);
1493 static unsigned int check_modem_status(struct uart_8250_port *up)
1495 unsigned int status = serial_in(up, UART_MSR);
1497 status |= up->msr_saved_flags;
1498 up->msr_saved_flags = 0;
1499 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1500 up->port.state != NULL) {
1502 up->port.icount.rng++;
1504 up->port.icount.dsr++;
1506 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1508 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1510 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1519 static void serial8250_handle_port(struct uart_8250_port *up)
1524 spin_lock_irqsave(&up->port.lock, flags);
1526 status = serial_inp(up, UART_LSR);
1531 receive_chars(up, &status);
1532 check_modem_status(up);
1534 transmit_chars(up);
1536 spin_unlock_irqrestore(&up->port.lock, flags);
1565 struct uart_8250_port *up;
1568 up = list_entry(l, struct uart_8250_port, list);
1570 iir = serial_in(up, UART_IIR);
1572 serial8250_handle_port(up);
1577 } else if (up->port.iotype == UPIO_DWAPB &&
1584 status = *(volatile u32 *)up->port.private_data;
1585 serial_out(up, UART_LCR, up->lcr);
1617 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1622 if (i->head == &up->list)
1624 list_del(&up->list);
1626 BUG_ON(i->head != &up->list);
1637 static int serial_link_irq_chain(struct uart_8250_port *up)
1642 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1646 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1650 if (i->irq == up->port.irq)
1661 i->irq = up->port.irq;
1669 list_add(&up->list, i->head);
1674 INIT_LIST_HEAD(&up->list);
1675 i->head = &up->list;
1677 irq_flags |= up->port.irqflags;
1678 ret = request_irq(up->port.irq, serial8250_interrupt,
1681 serial_do_unlink(i, up);
1687 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1695 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1699 if (i->irq == up->port.irq)
1707 free_irq(up->port.irq, i);
1709 serial_do_unlink(i, up);
1727 struct uart_8250_port *up = (struct uart_8250_port *)data;
1730 iir = serial_in(up, UART_IIR);
1732 serial8250_handle_port(up);
1733 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1738 struct uart_8250_port *up = (struct uart_8250_port *)data;
1746 if (is_real_interrupt(up->port.irq)) {
1747 ier = serial_in(up, UART_IER);
1748 serial_out(up, UART_IER, 0);
1751 iir = serial_in(up, UART_IIR);
1759 spin_lock_irqsave(&up->port.lock, flags);
1760 lsr = serial_in(up, UART_LSR);
1761 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1762 spin_unlock_irqrestore(&up->port.lock, flags);
1763 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1764 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1771 serial8250_handle_port(up);
1773 if (is_real_interrupt(up->port.irq))
1774 serial_out(up, UART_IER, ier);
1777 mod_timer(&up->timer,
1778 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1783 struct uart_8250_port *up = (struct uart_8250_port *)port;
1787 spin_lock_irqsave(&up->port.lock, flags);
1788 lsr = serial_in(up, UART_LSR);
1789 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1790 spin_unlock_irqrestore(&up->port.lock, flags);
1797 struct uart_8250_port *up = (struct uart_8250_port *)port;
1801 status = check_modem_status(up);
1817 struct uart_8250_port *up = (struct uart_8250_port *)port;
1831 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1833 serial_out(up, UART_MCR, mcr);
1838 struct uart_8250_port *up = (struct uart_8250_port *)port;
1841 spin_lock_irqsave(&up->port.lock, flags);
1843 up->lcr |= UART_LCR_SBC;
1845 up->lcr &= ~UART_LCR_SBC;
1846 serial_out(up, UART_LCR, up->lcr);
1847 spin_unlock_irqrestore(&up->port.lock, flags);
1853 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1857 /* Wait up to 10ms for the character(s) to be sent. */
1859 status = serial_in(up, UART_LSR);
1861 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1868 /* Wait up to 1s for flow control if necessary */
1869 if (up->port.flags & UPF_CONS_FLOW) {
1872 unsigned int msr = serial_in(up, UART_MSR);
1873 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1890 struct uart_8250_port *up = (struct uart_8250_port *)port;
1891 unsigned char lsr = serial_inp(up, UART_LSR);
1896 return serial_inp(up, UART_RX);
1904 struct uart_8250_port *up = (struct uart_8250_port *)port;
1909 ier = serial_in(up, UART_IER);
1910 if (up->capabilities & UART_CAP_UUE)
1911 serial_out(up, UART_IER, UART_IER_UUE);
1913 serial_out(up, UART_IER, 0);
1915 wait_for_xmitr(up, BOTH_EMPTY);
1920 serial_out(up, UART_TX, c);
1922 wait_for_xmitr(up, BOTH_EMPTY);
1923 serial_out(up, UART_TX, 13);
1930 wait_for_xmitr(up, BOTH_EMPTY);
1931 serial_out(up, UART_IER, ier);
1938 struct uart_8250_port *up = (struct uart_8250_port *)port;
1943 up->capabilities = uart_config[up->port.type].flags;
1944 up->mcr = 0;
1946 if (up->port.iotype != up->cur_iotype)
1949 if (up->port.type == PORT_16C950) {
1950 /* Wake up and initialize UART */
1951 up->acr = 0;
1952 serial_outp(up, UART_LCR, 0xBF);
1953 serial_outp(up, UART_EFR, UART_EFR_ECB);
1954 serial_outp(up, UART_IER, 0);
1955 serial_outp(up, UART_LCR, 0);
1956 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1957 serial_outp(up, UART_LCR, 0xBF);
1958 serial_outp(up, UART_EFR, UART_EFR_ECB);
1959 serial_outp(up, UART_LCR, 0);
1964 * If this is an RSA port, see if we can kick it up to the
1967 enable_rsa(up);
1974 serial8250_clear_fifos(up);
1979 (void) serial_inp(up, UART_LSR);
1980 (void) serial_inp(up, UART_RX);
1981 (void) serial_inp(up, UART_IIR);
1982 (void) serial_inp(up, UART_MSR);
1989 if (!(up->port.flags & UPF_BUGGY_UART) &&
1990 (serial_inp(up, UART_LSR) == 0xff)) {
1992 serial_index(&up->port));
1999 if (up->port.type == PORT_16850) {
2002 serial_outp(up, UART_LCR, 0xbf);
2004 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2005 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2006 serial_outp(up, UART_TRG, UART_TRG_96);
2007 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2008 serial_outp(up, UART_TRG, UART_TRG_96);
2010 serial_outp(up, UART_LCR, 0);
2013 if (is_real_interrupt(up->port.irq)) {
2023 spin_lock_irqsave(&up->port.lock, flags);
2024 if (up->port.irqflags & IRQF_SHARED)
2025 disable_irq_nosync(up->port.irq);
2027 wait_for_xmitr(up, UART_LSR_THRE);
2028 serial_out_sync(up, UART_IER, UART_IER_THRI);
2030 iir1 = serial_in(up, UART_IIR);
2031 serial_out(up, UART_IER, 0);
2032 serial_out_sync(up, UART_IER, UART_IER_THRI);
2034 iir = serial_in(up, UART_IIR);
2035 serial_out(up, UART_IER, 0);
2037 if (up->port.irqflags & IRQF_SHARED)
2038 enable_irq(up->port.irq);
2039 spin_unlock_irqrestore(&up->port.lock, flags);
2046 up->bugs |= UART_BUG_THRE;
2056 if (up->bugs & UART_BUG_THRE) {
2057 up->timer.function = serial8250_backup_timeout;
2058 up->timer.data = (unsigned long)up;
2059 mod_timer(&up->timer, jiffies +
2060 poll_timeout(up->port.timeout) + HZ / 5);
2068 if (!is_real_interrupt(up->port.irq)) {
2069 up->timer.data = (unsigned long)up;
2070 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2072 retval = serial_link_irq_chain(up);
2080 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2082 spin_lock_irqsave(&up->port.lock, flags);
2083 if (up->port.flags & UPF_FOURPORT) {
2084 if (!is_real_interrupt(up->port.irq))
2085 up->port.mctrl |= TIOCM_OUT1;
2090 if (is_real_interrupt(up->port.irq))
2091 up->port.mctrl |= TIOCM_OUT2;
2093 serial8250_set_mctrl(&up->port, up->port.mctrl);
2106 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2113 serial_outp(up, UART_IER, UART_IER_THRI);
2114 lsr = serial_in(up, UART_LSR);
2115 iir = serial_in(up, UART_IIR);
2116 serial_outp(up, UART_IER, 0);
2119 if (!(up->bugs & UART_BUG_TXEN)) {
2120 up->bugs |= UART_BUG_TXEN;
2125 up->bugs &= ~UART_BUG_TXEN;
2129 spin_unlock_irqrestore(&up->port.lock, flags);
2136 serial_inp(up, UART_LSR);
2137 serial_inp(up, UART_RX);
2138 serial_inp(up, UART_IIR);
2139 serial_inp(up, UART_MSR);
2140 up->lsr_saved_flags = 0;
2141 up->msr_saved_flags = 0;
2148 up->ier = UART_IER_RLSI | UART_IER_RDI;
2149 serial_outp(up, UART_IER, up->ier);
2151 if (up->port.flags & UPF_FOURPORT) {
2156 icp = (up->port.iobase & 0xfe0) | 0x01f;
2166 struct uart_8250_port *up = (struct uart_8250_port *)port;
2172 up->ier = 0;
2173 serial_outp(up, UART_IER, 0);
2175 spin_lock_irqsave(&up->port.lock, flags);
2176 if (up->port.flags & UPF_FOURPORT) {
2178 inb((up->port.iobase & 0xfe0) | 0x1f);
2179 up->port.mctrl |= TIOCM_OUT1;
2181 up->port.mctrl &= ~TIOCM_OUT2;
2183 serial8250_set_mctrl(&up->port, up->port.mctrl);
2184 spin_unlock_irqrestore(&up->port.lock, flags);
2189 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2190 serial8250_clear_fifos(up);
2196 disable_rsa(up);
2203 (void) serial_in(up, UART_RX);
2205 del_timer_sync(&up->timer);
2206 up->timer.function = serial8250_timeout;
2207 if (is_real_interrupt(up->port.irq))
2208 serial_unlink_irq_chain(up);
2235 struct uart_8250_port *up = (struct uart_8250_port *)port;
2275 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2278 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2282 fcr = uart_config[up->port.type].fcr;
2293 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2294 up->mcr &= ~UART_MCR_AFE;
2296 up->mcr |= UART_MCR_AFE;
2303 spin_lock_irqsave(&up->port.lock, flags);
2310 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2312 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2314 up->port.read_status_mask |= UART_LSR_BI;
2319 up->port.ignore_status_mask = 0;
2321 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2323 up->port.ignore_status_mask |= UART_LSR_BI;
2329 up->port.ignore_status_mask |= UART_LSR_OE;
2336 up->port.ignore_status_mask |= UART_LSR_DR;
2341 up->ier &= ~UART_IER_MSI;
2342 if (!(up->bugs & UART_BUG_NOMSR) &&
2343 UART_ENABLE_MS(&up->port, termios->c_cflag))
2344 up->ier |= UART_IER_MSI;
2345 if (up->capabilities & UART_CAP_UUE)
2346 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2348 serial_out(up, UART_IER, up->ier);
2350 if (up->capabilities & UART_CAP_EFR) {
2355 serial_outp(up, UART_LCR, 0xBF);
2356 serial_outp(up, UART_EFR, efr);
2360 if (cpu_is_omap1510() && is_omap_port(up)) {
2363 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2365 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2369 if (up->capabilities & UART_NATSEMI) {
2371 serial_outp(up, UART_LCR, 0xe0);
2373 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2376 serial_dl_write(up, quot);
2382 if (up->port.type == PORT_16750)
2383 serial_outp(up, UART_FCR, fcr);
2385 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2386 up->lcr = cval; /* Save LCR */
2387 if (up->port.type != PORT_16750) {
2390 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2392 serial_outp(up, UART_FCR, fcr); /* set fcr */
2394 serial8250_set_mctrl(&up->port, up->port.mctrl);
2395 spin_unlock_irqrestore(&up->port.lock, flags);
2448 static int serial8250_request_std_resource(struct uart_8250_port *up)
2450 unsigned int size = serial8250_port_size(up);
2453 switch (up->port.iotype) {
2459 if (!up->port.mapbase)
2462 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2467 if (up->port.flags & UPF_IOREMAP) {
2468 up->port.membase = ioremap_nocache(up->port.mapbase,
2470 if (!up->port.membase) {
2471 release_mem_region(up->port.mapbase, size);
2479 if (!request_region(up->port.iobase, size, "serial"))
2486 static void serial8250_release_std_resource(struct uart_8250_port *up)
2488 unsigned int size = serial8250_port_size(up);
2490 switch (up->port.iotype) {
2496 if (!up->port.mapbase)
2499 if (up->port.flags & UPF_IOREMAP) {
2500 iounmap(up->port.membase);
2501 up->port.membase = NULL;
2504 release_mem_region(up->port.mapbase, size);
2509 release_region(up->port.iobase, size);
2514 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2516 unsigned long start = UART_RSA_BASE << up->port.regshift;
2517 unsigned int size = 8 << up->port.regshift;
2520 switch (up->port.iotype) {
2523 start += up->port.iobase;
2534 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2536 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2537 unsigned int size = 8 << up->port.regshift;
2539 switch (up->port.iotype) {
2542 release_region(up->port.iobase + offset, size);
2549 struct uart_8250_port *up = (struct uart_8250_port *)port;
2551 serial8250_release_std_resource(up);
2552 if (up->port.type == PORT_RSA)
2553 serial8250_release_rsa_resource(up);
2558 struct uart_8250_port *up = (struct uart_8250_port *)port;
2561 ret = serial8250_request_std_resource(up);
2562 if (ret == 0 && up->port.type == PORT_RSA) {
2563 ret = serial8250_request_rsa_resource(up);
2565 serial8250_release_std_resource(up);
2573 struct uart_8250_port *up = (struct uart_8250_port *)port;
2581 ret = serial8250_request_std_resource(up);
2585 ret = serial8250_request_rsa_resource(up);
2589 if (up->port.iotype != up->cur_iotype)
2593 autoconfig(up, probeflags);
2596 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2597 up->bugs |= UART_BUG_NOMSR;
2599 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2600 autoconfig_irq(up);
2602 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2603 serial8250_release_rsa_resource(up);
2604 if (up->port.type == PORT_UNKNOWN)
2605 serial8250_release_std_resource(up);
2658 struct uart_8250_port *up;
2667 struct uart_8250_port *up = &serial8250_ports[i];
2669 up->port.line = i;
2670 spin_lock_init(&up->port.lock);
2672 init_timer(&up->timer);
2673 up->timer.function = serial8250_timeout;
2678 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2679 up->mcr_force = ALPHA_KLUDGE_MCR;
2681 up->port.ops = &serial8250_pops;
2687 for (i = 0, up = serial8250_ports;
2689 i++, up++) {
2690 up->port.iobase = old_serial_port[i].port;
2691 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2692 up->port.irqflags = old_serial_port[i].irqflags;
2693 up->port.uartclk = old_serial_port[i].baud_base * 16;
2694 up->port.flags = old_serial_port[i].flags;
2695 up->port.hub6 = old_serial_port[i].hub6;
2696 up->port.membase = old_serial_port[i].iomem_base;
2697 up->port.iotype = old_serial_port[i].io_type;
2698 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2699 set_io_from_upio(&up->port);
2700 up->port.irqflags |= irqflag;
2705 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2707 up->port.type = type;
2708 up->port.fifosize = uart_config[type].fifo_size;
2709 up->capabilities = uart_config[type].flags;
2710 up->tx_loadsz = uart_config[type].tx_loadsz;
2719 struct uart_8250_port *up = &serial8250_ports[i];
2720 up->cur_iotype = 0xFF;
2726 struct uart_8250_port *up = &serial8250_ports[i];
2728 up->port.dev = dev;
2730 if (up->port.flags & UPF_FIXED_TYPE)
2731 serial8250_init_fixed_type_port(up, up->port.type);
2733 uart_add_one_port(drv, &up->port);
2741 struct uart_8250_port *up = (struct uart_8250_port *)port;
2743 wait_for_xmitr(up, UART_LSR_THRE);
2744 serial_out(up, UART_TX, ch);
2756 struct uart_8250_port *up = &serial8250_ports[co->index];
2764 if (up->port.sysrq) {
2768 locked = spin_trylock(&up->port.lock);
2770 spin_lock(&up->port.lock);
2775 ier = serial_in(up, UART_IER);
2777 if (up->capabilities & UART_CAP_UUE)
2778 serial_out(up, UART_IER, UART_IER_UUE);
2780 serial_out(up, UART_IER, 0);
2782 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2788 wait_for_xmitr(up, BOTH_EMPTY);
2789 serial_out(up, UART_IER, ier);
2798 if (up->msr_saved_flags)
2799 check_modem_status(up);
2802 spin_unlock(&up->port.lock);
2942 struct uart_8250_port *up = &serial8250_ports[line];
2944 if (up->capabilities & UART_NATSEMI) {
2948 serial_outp(up, UART_LCR, 0xE0);
2950 tmp = serial_in(up, 0x04); /* EXCR2 */
2953 serial_outp(up, 0x04, tmp);
2955 serial_outp(up, UART_LCR, 0);
2957 uart_resume_port(&serial8250_reg, &up->port);
3013 struct uart_8250_port *up = &serial8250_ports[i];
3015 if (up->port.dev == &dev->dev)
3026 struct uart_8250_port *up = &serial8250_ports[i];
3028 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3029 uart_suspend_port(&serial8250_reg, &up->port);
3040 struct uart_8250_port *up = &serial8250_ports[i];
3042 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3110 * port exists and is in use, it is hung up and unregistered