Lines Matching defs:mem_crb
1267 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1274 mem_crb = QLA82XX_CRB_QDR_NET;
1276 mem_crb = QLA82XX_CRB_DDR_NET;
1298 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1300 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1302 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1304 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1307 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1323 mem_crb + MIU_TEST_AGT_RDDATA(k));
1367 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1373 mem_crb = QLA82XX_CRB_QDR_NET;
1375 mem_crb = QLA82XX_CRB_DDR_NET;
1432 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1434 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1436 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1438 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1440 qla82xx_wr_32(ha, mem_crb +
1443 qla82xx_wr_32(ha, mem_crb +
1447 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1449 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1452 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);