Lines Matching refs:mvi
85 static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
87 struct mvs_phy *phy = &mvi->phy[phy_id];
90 phy->mvi = mvi;
92 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
102 sas_phy->sas_addr = &mvi->sas_addr[0];
104 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
108 static void mvs_free(struct mvs_info *mvi)
114 if (!mvi)
117 if (mvi->flags & MVF_FLAG_SOC)
122 for (i = 0; i < mvi->tags_num; i++) {
123 struct mvs_slot_info *slot = &mvi->slot_info[i];
125 dma_free_coherent(mvi->dev, MVS_SLOT_BUF_SZ,
129 if (mvi->tx)
130 dma_free_coherent(mvi->dev,
131 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
132 mvi->tx, mvi->tx_dma);
133 if (mvi->rx_fis)
134 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
135 mvi->rx_fis, mvi->rx_fis_dma);
136 if (mvi->rx)
137 dma_free_coherent(mvi->dev,
138 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
139 mvi->rx, mvi->rx_dma);
140 if (mvi->slot)
141 dma_free_coherent(mvi->dev,
142 sizeof(*mvi->slot) * slot_nr,
143 mvi->slot, mvi->slot_dma);
145 if (mvi->bulk_buffer)
146 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
147 mvi->bulk_buffer, mvi->bulk_buffer_dma);
150 MVS_CHIP_DISP->chip_iounmap(mvi);
151 if (mvi->shost)
152 scsi_host_put(mvi->shost);
153 list_for_each_entry(mwq, &mvi->wq_list, entry)
155 kfree(mvi);
166 struct mvs_info *mvi;
170 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
172 if (unlikely(!mvi))
176 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
177 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->irq);
179 MVS_CHIP_DISP->isr(mvi, mvi->irq, stat);
189 struct mvs_info *mvi;
193 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
195 if (unlikely(!mvi))
198 stat = MVS_CHIP_DISP->isr_status(mvi, irq);
206 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
207 MVS_CHIP_DISP->isr(mvi, irq, stat);
213 static int __devinit mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
217 if (mvi->flags & MVF_FLAG_SOC)
222 spin_lock_init(&mvi->lock);
223 for (i = 0; i < mvi->chip->n_phy; i++) {
224 mvs_phy_init(mvi, i);
225 mvi->port[i].wide_port_phymap = 0;
226 mvi->port[i].port_attached = 0;
227 INIT_LIST_HEAD(&mvi->port[i].list);
230 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
231 mvi->devices[i].dev_type = NO_DEVICE;
232 mvi->devices[i].device_id = i;
233 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
234 init_timer(&mvi->devices[i].timer);
240 mvi->tx = dma_alloc_coherent(mvi->dev,
241 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
242 &mvi->tx_dma, GFP_KERNEL);
243 if (!mvi->tx)
245 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
246 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
247 &mvi->rx_fis_dma, GFP_KERNEL);
248 if (!mvi->rx_fis)
250 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
252 mvi->rx = dma_alloc_coherent(mvi->dev,
253 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
254 &mvi->rx_dma, GFP_KERNEL);
255 if (!mvi->rx)
257 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
258 mvi->rx[0] = cpu_to_le32(0xfff);
259 mvi->rx_cons = 0xfff;
261 mvi->slot = dma_alloc_coherent(mvi->dev,
262 sizeof(*mvi->slot) * slot_nr,
263 &mvi->slot_dma, GFP_KERNEL);
264 if (!mvi->slot)
266 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
269 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
271 &mvi->bulk_buffer_dma, GFP_KERNEL);
272 if (!mvi->bulk_buffer)
276 struct mvs_slot_info *slot = &mvi->slot_info[i];
278 slot->buf = dma_alloc_coherent(mvi->dev, MVS_SLOT_BUF_SZ,
285 ++mvi->tags_num;
288 mvs_tag_init(mvi);
295 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
298 struct pci_dev *pdev = mvi->pdev;
311 mvi->regs_ex = ioremap(res_start, res_len);
313 mvi->regs_ex = ioremap_nocache(res_start,
316 mvi->regs_ex = (void *)res_start;
317 if (!mvi->regs_ex)
328 mvi->regs = ioremap(res_start, res_len);
330 mvi->regs = ioremap_nocache(res_start, res_len);
332 if (!mvi->regs) {
333 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
334 iounmap(mvi->regs_ex);
335 mvi->regs_ex = NULL;
353 struct mvs_info *mvi;
356 mvi = kzalloc(sizeof(*mvi) + MVS_SLOTS * sizeof(struct mvs_slot_info),
358 if (!mvi)
361 mvi->pdev = pdev;
362 mvi->dev = &pdev->dev;
363 mvi->chip_id = ent->driver_data;
364 mvi->chip = &mvs_chips[mvi->chip_id];
365 INIT_LIST_HEAD(&mvi->wq_list);
366 mvi->irq = pdev->irq;
368 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
369 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
371 mvi->id = id;
372 mvi->sas = sha;
373 mvi->shost = shost;
378 if (MVS_CHIP_DISP->chip_ioremap(mvi))
380 if (!mvs_alloc(mvi, shost))
381 return mvi;
383 mvs_free(mvi);
466 struct mvs_info *mvi = NULL;
471 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
474 &mvi->phy[i].sas_phy;
476 &mvi->port[i].sas_port;
481 sha->dev = mvi->dev;
483 sha->sas_addr = &mvi->sas_addr[0];
489 if (mvi->flags & MVF_FLAG_SOC)
496 mvi->shost->cmd_per_lun = MVS_SLOTS/sha->num_phys;
497 sha->core.shost = mvi->shost;
500 static void mvs_init_sas_add(struct mvs_info *mvi)
503 for (i = 0; i < mvi->chip->n_phy; i++) {
504 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
505 mvi->phy[i].dev_sas_addr =
506 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
509 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
516 struct mvs_info *mvi;
562 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
563 if (!mvi) {
568 mvs_init_sas_add(mvi);
570 mvi->instance = nhost;
571 rc = MVS_CHIP_DISP->chip_init(mvi);
573 mvs_free(mvi);
597 MVS_CHIP_DISP->interrupt_enable(mvi);
599 scsi_scan_host(mvi->shost);
606 scsi_remove_host(mvi->shost);
619 struct mvs_info *mvi = NULL;
622 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
630 sas_remove_host(mvi->shost);
631 scsi_remove_host(mvi->shost);
633 MVS_CHIP_DISP->interrupt_disable(mvi);
634 free_irq(mvi->irq, sha);
636 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
637 mvs_free(mvi);