Lines Matching refs:status_reg_value
43 static int tw_check_bits(u32 status_reg_value)
45 if ((status_reg_value & TW_STATUS_EXPECTED_BITS) != TW_STATUS_EXPECTED_BITS) {
46 dprintk(KERN_WARNING "3w-xxxx: tw_check_bits(): No expected bits (0x%x).\n", status_reg_value);
49 if ((status_reg_value & TW_STATUS_UNEXPECTED_BITS) != 0) {
50 dprintk(KERN_WARNING "3w-xxxx: tw_check_bits(): Found unexpected bits (0x%x).\n", status_reg_value);
58 static int tw_decode_bits(TW_Device_Extension *tw_dev, u32 status_reg_value, int print_host)
69 if (status_reg_value & TW_STATUS_PCI_PARITY_ERROR) {
74 if (status_reg_value & TW_STATUS_PCI_ABORT) {
80 if (status_reg_value & TW_STATUS_QUEUE_ERROR) {
85 if (status_reg_value & TW_STATUS_SBUF_WRITE_ERROR) {
90 if (status_reg_value & TW_STATUS_MICROCONTROLLER_ERROR) {
104 u32 status_reg_value;
108 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
111 if (tw_check_bits(status_reg_value))
112 tw_decode_bits(tw_dev, status_reg_value, 0);
114 while ((status_reg_value & flag) != flag) {
115 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
117 if (tw_check_bits(status_reg_value))
118 tw_decode_bits(tw_dev, status_reg_value, 0);
133 u32 status_reg_value;
137 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
140 if (tw_check_bits(status_reg_value))
141 tw_decode_bits(tw_dev, status_reg_value, 0);
143 while ((status_reg_value & flag) != 0) {
144 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
146 if (tw_check_bits(status_reg_value))
147 tw_decode_bits(tw_dev, status_reg_value, 0);
162 u32 status_reg_value;
167 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
169 if (tw_check_bits(status_reg_value)) {
171 tw_decode_bits(tw_dev, status_reg_value, 1);
174 if ((status_reg_value & TW_STATUS_COMMAND_QUEUE_FULL) == 0) {
251 u32 status_reg_value;
253 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
255 if (TW_STATUS_ERRORS(status_reg_value) || tw_check_bits(status_reg_value)) {
256 tw_decode_bits(tw_dev, status_reg_value, 0);
266 u32 status_reg_value, response_que_value;
268 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
270 while ((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) {
272 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
362 u32 status_reg_value;
367 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
368 if (tw_check_bits(status_reg_value)) {
370 tw_decode_bits(tw_dev, status_reg_value, 1);
409 if ((status_reg_value & TW_STATUS_COMMAND_QUEUE_FULL) == 0) {
1833 u32 status_reg_value;
1844 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
1847 if (!(status_reg_value & TW_STATUS_VALID_INTERRUPT))
1857 if (tw_check_bits(status_reg_value)) {
1859 if (tw_decode_bits(tw_dev, status_reg_value, 1)) {
1866 if (status_reg_value & TW_STATUS_HOST_INTERRUPT) {
1872 if (status_reg_value & TW_STATUS_ATTENTION_INTERRUPT) {
1885 if (status_reg_value & TW_STATUS_COMMAND_INTERRUPT) {
1911 if (status_reg_value & TW_STATUS_RESPONSE_INTERRUPT) {
1913 while ((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) {
2010 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
2011 if (tw_check_bits(status_reg_value)) {
2013 if (tw_decode_bits(tw_dev, status_reg_value, 1)) {