Lines Matching refs:wl1271_write32
101 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
265 wl1271_write32(wl, dest_addr, val);
299 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
301 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
310 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
331 wl1271_write32(wl, ENABLE, 0x0);
334 wl1271_write32(wl, SPARE_A2, 0xffff);
368 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
478 wl1271_write32(wl, PLL_PARAMETERS, clk);
486 wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
489 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
505 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
510 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
525 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
538 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,