Lines Matching defs:ugeth
208 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
213 skb = __skb_dequeue(&ugeth->rx_recycle);
215 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
228 skb->dev = ugeth->ndev;
231 dma_map_single(ugeth->dev,
233 ugeth->ug_info->uf_info.max_rx_buf_length +
243 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
250 bd = ugeth->p_rx_bd_ring[rxQ];
255 skb = get_new_skb(ugeth, bd);
261 ugeth->rx_skbuff[rxQ][i] = skb;
271 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
285 if (netif_msg_ifup(ugeth))
296 if (netif_msg_ifup(ugeth))
310 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
344 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
397 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
407 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
419 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
426 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
430 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
448 static void get_statistics(struct ucc_geth_private *ugeth,
460 ug_regs = ugeth->ug_regs;
462 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
463 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
568 static void dump_bds(struct ucc_geth_private *ugeth)
573 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
574 if (ugeth->p_tx_bd_ring[i]) {
576 (ugeth->ug_info->bdRingLenTx[i] *
579 mem_disp(ugeth->p_tx_bd_ring[i], length);
582 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
583 if (ugeth->p_rx_bd_ring[i]) {
585 (ugeth->ug_info->bdRingLenRx[i] *
588 mem_disp(ugeth->p_rx_bd_ring[i], length);
593 static void dump_regs(struct ucc_geth_private *ugeth)
597 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num + 1);
598 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
601 (u32) & ugeth->ug_regs->maccfg1,
602 in_be32(&ugeth->ug_regs->maccfg1));
604 (u32) & ugeth->ug_regs->maccfg2,
605 in_be32(&ugeth->ug_regs->maccfg2));
607 (u32) & ugeth->ug_regs->ipgifg,
608 in_be32(&ugeth->ug_regs->ipgifg));
610 (u32) & ugeth->ug_regs->hafdup,
611 in_be32(&ugeth->ug_regs->hafdup));
613 (u32) & ugeth->ug_regs->ifctl,
614 in_be32(&ugeth->ug_regs->ifctl));
616 (u32) & ugeth->ug_regs->ifstat,
617 in_be32(&ugeth->ug_regs->ifstat));
619 (u32) & ugeth->ug_regs->macstnaddr1,
620 in_be32(&ugeth->ug_regs->macstnaddr1));
622 (u32) & ugeth->ug_regs->macstnaddr2,
623 in_be32(&ugeth->ug_regs->macstnaddr2));
625 (u32) & ugeth->ug_regs->uempr,
626 in_be32(&ugeth->ug_regs->uempr));
628 (u32) & ugeth->ug_regs->utbipar,
629 in_be32(&ugeth->ug_regs->utbipar));
631 (u32) & ugeth->ug_regs->uescr,
632 in_be16(&ugeth->ug_regs->uescr));
634 (u32) & ugeth->ug_regs->tx64,
635 in_be32(&ugeth->ug_regs->tx64));
637 (u32) & ugeth->ug_regs->tx127,
638 in_be32(&ugeth->ug_regs->tx127));
640 (u32) & ugeth->ug_regs->tx255,
641 in_be32(&ugeth->ug_regs->tx255));
643 (u32) & ugeth->ug_regs->rx64,
644 in_be32(&ugeth->ug_regs->rx64));
646 (u32) & ugeth->ug_regs->rx127,
647 in_be32(&ugeth->ug_regs->rx127));
649 (u32) & ugeth->ug_regs->rx255,
650 in_be32(&ugeth->ug_regs->rx255));
652 (u32) & ugeth->ug_regs->txok,
653 in_be32(&ugeth->ug_regs->txok));
655 (u32) & ugeth->ug_regs->txcf,
656 in_be16(&ugeth->ug_regs->txcf));
658 (u32) & ugeth->ug_regs->tmca,
659 in_be32(&ugeth->ug_regs->tmca));
661 (u32) & ugeth->ug_regs->tbca,
662 in_be32(&ugeth->ug_regs->tbca));
664 (u32) & ugeth->ug_regs->rxfok,
665 in_be32(&ugeth->ug_regs->rxfok));
667 (u32) & ugeth->ug_regs->rxbok,
668 in_be32(&ugeth->ug_regs->rxbok));
670 (u32) & ugeth->ug_regs->rbyt,
671 in_be32(&ugeth->ug_regs->rbyt));
673 (u32) & ugeth->ug_regs->rmca,
674 in_be32(&ugeth->ug_regs->rmca));
676 (u32) & ugeth->ug_regs->rbca,
677 in_be32(&ugeth->ug_regs->rbca));
679 (u32) & ugeth->ug_regs->scar,
680 in_be32(&ugeth->ug_regs->scar));
682 (u32) & ugeth->ug_regs->scam,
683 in_be32(&ugeth->ug_regs->scam));
685 if (ugeth->p_thread_data_tx) {
687 switch (ugeth->ug_info->numThreadsTx) {
710 (u32) ugeth->p_thread_data_tx);
714 (u32) & ugeth->p_thread_data_tx[i]);
715 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
719 if (ugeth->p_thread_data_rx) {
721 switch (ugeth->ug_info->numThreadsRx) {
744 (u32) ugeth->p_thread_data_rx);
748 (u32) & ugeth->p_thread_data_rx[i]);
749 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
753 if (ugeth->p_exf_glbl_param) {
756 (u32) ugeth->p_exf_glbl_param);
757 mem_disp((u8 *) ugeth->p_exf_glbl_param,
758 sizeof(*ugeth->p_exf_glbl_param));
760 if (ugeth->p_tx_glbl_pram) {
762 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
764 (u32) & ugeth->p_tx_glbl_pram->temoder,
765 in_be16(&ugeth->p_tx_glbl_pram->temoder));
767 (u32) & ugeth->p_tx_glbl_pram->sqptr,
768 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
770 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
771 in_be32(&ugeth->p_tx_glbl_pram->
774 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
775 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
777 (u32) & ugeth->p_tx_glbl_pram->tstate,
778 in_be32(&ugeth->p_tx_glbl_pram->tstate));
780 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
781 ugeth->p_tx_glbl_pram->iphoffset[0]);
783 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
784 ugeth->p_tx_glbl_pram->iphoffset[1]);
786 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
787 ugeth->p_tx_glbl_pram->iphoffset[2]);
789 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
790 ugeth->p_tx_glbl_pram->iphoffset[3]);
792 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
793 ugeth->p_tx_glbl_pram->iphoffset[4]);
795 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
796 ugeth->p_tx_glbl_pram->iphoffset[5]);
798 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
799 ugeth->p_tx_glbl_pram->iphoffset[6]);
801 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
802 ugeth->p_tx_glbl_pram->iphoffset[7]);
804 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
805 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
807 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
808 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
810 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
811 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
813 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
814 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
816 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
817 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
819 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
820 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
822 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
823 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
825 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
826 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
828 (u32) & ugeth->p_tx_glbl_pram->tqptr,
829 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
831 if (ugeth->p_rx_glbl_pram) {
833 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
835 (u32) & ugeth->p_rx_glbl_pram->remoder,
836 in_be32(&ugeth->p_rx_glbl_pram->remoder));
838 (u32) & ugeth->p_rx_glbl_pram->rqptr,
839 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
841 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
842 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
844 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
845 ugeth->p_rx_glbl_pram->rxgstpack);
847 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
848 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
850 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
851 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
853 (u32) & ugeth->p_rx_glbl_pram->rstate,
854 ugeth->p_rx_glbl_pram->rstate);
856 (u32) & ugeth->p_rx_glbl_pram->mrblr,
857 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
859 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
860 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
862 (u32) & ugeth->p_rx_glbl_pram->mflr,
863 in_be16(&ugeth->p_rx_glbl_pram->mflr));
865 (u32) & ugeth->p_rx_glbl_pram->minflr,
866 in_be16(&ugeth->p_rx_glbl_pram->minflr));
868 (u32) & ugeth->p_rx_glbl_pram->maxd1,
869 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
871 (u32) & ugeth->p_rx_glbl_pram->maxd2,
872 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
874 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
875 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
877 (u32) & ugeth->p_rx_glbl_pram->l2qt,
878 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
880 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
881 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
883 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
884 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
886 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
887 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
889 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
890 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
892 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
893 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
895 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
896 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
898 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
899 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
901 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
902 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
904 (u32) & ugeth->p_rx_glbl_pram->vlantype,
905 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
907 (u32) & ugeth->p_rx_glbl_pram->vlantci,
908 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
913 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
914 ugeth->p_rx_glbl_pram->addressfiltering[i]);
916 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
917 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
919 if (ugeth->p_send_q_mem_reg) {
922 (u32) ugeth->p_send_q_mem_reg);
923 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
926 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
927 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
931 if (ugeth->p_scheduler) {
933 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
934 mem_disp((u8 *) ugeth->p_scheduler,
935 sizeof(*ugeth->p_scheduler));
937 if (ugeth->p_tx_fw_statistics_pram) {
940 (u32) ugeth->p_tx_fw_statistics_pram);
941 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
942 sizeof(*ugeth->p_tx_fw_statistics_pram));
944 if (ugeth->p_rx_fw_statistics_pram) {
947 (u32) ugeth->p_rx_fw_statistics_pram);
948 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
949 sizeof(*ugeth->p_rx_fw_statistics_pram));
951 if (ugeth->p_rx_irq_coalescing_tbl) {
954 (u32) ugeth->p_rx_irq_coalescing_tbl);
955 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
958 (u32) & ugeth->p_rx_irq_coalescing_tbl->
962 (u32) & ugeth->p_rx_irq_coalescing_tbl->
964 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
969 (u32) & ugeth->p_rx_irq_coalescing_tbl->
971 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
976 if (ugeth->p_rx_bd_qs_tbl) {
978 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
979 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
982 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
985 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
986 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
989 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
990 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
993 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
994 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
998 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
999 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1004 (&ugeth->p_rx_bd_qs_tbl[i].
1008 (&ugeth->p_rx_bd_qs_tbl[i].
1013 if (ugeth->p_init_enet_param_shadow) {
1017 (u32) ugeth->p_init_enet_param_shadow);
1018 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1019 sizeof(*ugeth->p_init_enet_param_shadow));
1022 if (ugeth->ug_info->rxExtendedFiltering) {
1025 if (ugeth->ug_info->largestexternallookupkeysize ==
1029 if (ugeth->ug_info->largestexternallookupkeysize ==
1035 dump_init_enet_entries(ugeth,
1036 &(ugeth->p_init_enet_param_shadow->
1040 ugeth->ug_info->riscTx, 0);
1041 dump_init_enet_entries(ugeth,
1042 &(ugeth->p_init_enet_param_shadow->
1045 ugeth->ug_info->riscRx, 1);
1332 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1343 ug_info = ugeth->ug_info;
1344 ug_regs = ugeth->ug_regs;
1345 uf_regs = ugeth->uccf->uf_regs;
1350 if ((ugeth->max_speed == SPEED_10) ||
1351 (ugeth->max_speed == SPEED_100))
1353 else if (ugeth->max_speed == SPEED_1000)
1362 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1363 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1364 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1365 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1366 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1367 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1368 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1370 switch (ugeth->max_speed) {
1375 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1379 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1380 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1383 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1391 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1392 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1393 struct ucc_geth_info *ug_info = ugeth->ug_info;
1413 if (netif_msg_probe(ugeth))
1422 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1429 uccf = ugeth->uccf;
1437 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1452 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1459 uccf = ugeth->uccf;
1462 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1464 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1471 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1476 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1484 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1489 uccf = ugeth->uccf;
1492 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1499 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1504 uccf = ugeth->uccf;
1507 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1515 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1520 uccf = ugeth->uccf;
1523 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1524 if (netif_msg_probe(ugeth))
1535 ugeth_restart_tx(ugeth);
1537 ugeth_restart_rx(ugeth);
1545 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1549 uccf = ugeth->uccf;
1552 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1553 if (netif_msg_probe(ugeth))
1560 ugeth_graceful_stop_tx(ugeth);
1564 ugeth_graceful_stop_rx(ugeth);
1566 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1571 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1574 netif_device_detach(ugeth->ndev);
1577 netif_tx_disable(ugeth->ndev);
1580 disable_irq(ugeth->ug_info->uf_info.irq);
1583 napi_disable(&ugeth->napi);
1586 static void ugeth_activate(struct ucc_geth_private *ugeth)
1588 napi_enable(&ugeth->napi);
1589 enable_irq(ugeth->ug_info->uf_info.irq);
1590 netif_device_attach(ugeth->ndev);
1595 * information through variables in the ugeth structure, and this
1602 struct ucc_geth_private *ugeth = netdev_priv(dev);
1605 struct phy_device *phydev = ugeth->phydev;
1608 ug_regs = ugeth->ug_regs;
1609 uf_regs = ugeth->uccf->uf_regs;
1616 if (phydev->duplex != ugeth->oldduplex) {
1622 ugeth->oldduplex = phydev->duplex;
1625 if (phydev->speed != ugeth->oldspeed) {
1639 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1640 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1641 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1642 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1643 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1644 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1652 if (netif_msg_link(ugeth))
1658 ugeth->oldspeed = phydev->speed;
1661 if (!ugeth->oldlink) {
1663 ugeth->oldlink = 1;
1670 * ugeth->lock, which is a bad idea since 'graceful
1674 ugeth_quiesce(ugeth);
1675 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1680 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1681 ugeth_activate(ugeth);
1683 } else if (ugeth->oldlink) {
1685 ugeth->oldlink = 0;
1686 ugeth->oldspeed = 0;
1687 ugeth->oldduplex = -1;
1690 if (new_state && netif_msg_link(ugeth))
1704 struct ucc_geth_private *ugeth = netdev_priv(dev);
1705 struct ucc_geth_info *ug_info = ugeth->ug_info;
1778 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1781 ucc_fast_dump_regs(ugeth->uccf);
1782 dump_regs(ugeth);
1783 dump_bds(ugeth);
1788 ugeth,
1801 uccf = ugeth->uccf;
1805 ugeth->p_rx_glbl_pram->addressfiltering;
1810 p_lh = &ugeth->group_hash_q;
1811 p_counter = &(ugeth->numGroupAddrInHash);
1815 p_lh = &ugeth->ind_hash_q;
1816 p_counter = &(ugeth->numIndAddrInHash);
1826 ugeth_disable(ugeth, comm_dir);
1844 ugeth_enable(ugeth, comm_dir);
1849 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1852 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1853 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1856 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1861 if (!ugeth)
1864 if (ugeth->uccf) {
1865 ucc_fast_free(ugeth->uccf);
1866 ugeth->uccf = NULL;
1869 if (ugeth->p_thread_data_tx) {
1870 qe_muram_free(ugeth->thread_dat_tx_offset);
1871 ugeth->p_thread_data_tx = NULL;
1873 if (ugeth->p_thread_data_rx) {
1874 qe_muram_free(ugeth->thread_dat_rx_offset);
1875 ugeth->p_thread_data_rx = NULL;
1877 if (ugeth->p_exf_glbl_param) {
1878 qe_muram_free(ugeth->exf_glbl_param_offset);
1879 ugeth->p_exf_glbl_param = NULL;
1881 if (ugeth->p_rx_glbl_pram) {
1882 qe_muram_free(ugeth->rx_glbl_pram_offset);
1883 ugeth->p_rx_glbl_pram = NULL;
1885 if (ugeth->p_tx_glbl_pram) {
1886 qe_muram_free(ugeth->tx_glbl_pram_offset);
1887 ugeth->p_tx_glbl_pram = NULL;
1889 if (ugeth->p_send_q_mem_reg) {
1890 qe_muram_free(ugeth->send_q_mem_reg_offset);
1891 ugeth->p_send_q_mem_reg = NULL;
1893 if (ugeth->p_scheduler) {
1894 qe_muram_free(ugeth->scheduler_offset);
1895 ugeth->p_scheduler = NULL;
1897 if (ugeth->p_tx_fw_statistics_pram) {
1898 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1899 ugeth->p_tx_fw_statistics_pram = NULL;
1901 if (ugeth->p_rx_fw_statistics_pram) {
1902 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1903 ugeth->p_rx_fw_statistics_pram = NULL;
1905 if (ugeth->p_rx_irq_coalescing_tbl) {
1906 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1907 ugeth->p_rx_irq_coalescing_tbl = NULL;
1909 if (ugeth->p_rx_bd_qs_tbl) {
1910 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1911 ugeth->p_rx_bd_qs_tbl = NULL;
1913 if (ugeth->p_init_enet_param_shadow) {
1914 return_init_enet_entries(ugeth,
1915 &(ugeth->p_init_enet_param_shadow->
1918 ugeth->ug_info->riscRx, 1);
1919 return_init_enet_entries(ugeth,
1920 &(ugeth->p_init_enet_param_shadow->
1923 ugeth->ug_info->riscTx, 0);
1924 kfree(ugeth->p_init_enet_param_shadow);
1925 ugeth->p_init_enet_param_shadow = NULL;
1927 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1928 bd = ugeth->p_tx_bd_ring[i];
1931 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1932 if (ugeth->tx_skbuff[i][j]) {
1933 dma_unmap_single(ugeth->dev,
1938 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1939 ugeth->tx_skbuff[i][j] = NULL;
1943 kfree(ugeth->tx_skbuff[i]);
1945 if (ugeth->p_tx_bd_ring[i]) {
1946 if (ugeth->ug_info->uf_info.bd_mem_part ==
1948 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1949 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1951 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1952 ugeth->p_tx_bd_ring[i] = NULL;
1955 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1956 if (ugeth->p_rx_bd_ring[i]) {
1958 bd = ugeth->p_rx_bd_ring[i];
1959 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1960 if (ugeth->rx_skbuff[i][j]) {
1961 dma_unmap_single(ugeth->dev,
1963 ugeth->ug_info->
1968 ugeth->rx_skbuff[i][j]);
1969 ugeth->rx_skbuff[i][j] = NULL;
1974 kfree(ugeth->rx_skbuff[i]);
1976 if (ugeth->ug_info->uf_info.bd_mem_part ==
1978 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1979 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1981 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1982 ugeth->p_rx_bd_ring[i] = NULL;
1985 while (!list_empty(&ugeth->group_hash_q))
1987 (dequeue(&ugeth->group_hash_q)));
1988 while (!list_empty(&ugeth->ind_hash_q))
1990 (dequeue(&ugeth->ind_hash_q)));
1991 if (ugeth->ug_regs) {
1992 iounmap(ugeth->ug_regs);
1993 ugeth->ug_regs = NULL;
1996 skb_queue_purge(&ugeth->rx_recycle);
2001 struct ucc_geth_private *ugeth;
2006 ugeth = netdev_priv(dev);
2008 uf_regs = ugeth->uccf->uf_regs;
2016 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2040 hw_add_addr_in_hash(ugeth, ha->addr);
2046 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2048 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2049 struct phy_device *phydev = ugeth->phydev;
2054 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2060 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2063 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2068 phy_disconnect(ugeth->phydev);
2069 ugeth->phydev = NULL;
2071 ucc_geth_memclean(ugeth);
2074 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2080 ug_info = ugeth->ug_info;
2085 if (netif_msg_probe(ugeth))
2096 if (netif_msg_probe(ugeth))
2107 if (netif_msg_probe(ugeth))
2118 if (netif_msg_probe(ugeth))
2127 if (netif_msg_probe(ugeth))
2134 if (netif_msg_probe(ugeth))
2142 if (netif_msg_probe(ugeth))
2154 if (netif_msg_probe(ugeth))
2164 if (netif_msg_probe(ugeth))
2173 if (netif_msg_probe(ugeth))
2188 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2189 if (netif_msg_probe(ugeth))
2202 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2203 if (!ugeth->ug_regs) {
2204 if (netif_msg_probe(ugeth))
2209 skb_queue_head_init(&ugeth->rx_recycle);
2214 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2235 uccf = ugeth->uccf;
2236 ug_info = ugeth->ug_info;
2239 ug_regs = ugeth->ug_regs;
2258 if (netif_msg_ifup(ugeth))
2282 if (netif_msg_ifup(ugeth))
2290 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2295 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2332 if (netif_msg_ifup(ugeth))
2349 if (netif_msg_ifup(ugeth))
2385 ugeth->tx_bd_ring_offset[j] =
2388 if (ugeth->tx_bd_ring_offset[j] != 0)
2389 ugeth->p_tx_bd_ring[j] =
2390 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2393 ugeth->tx_bd_ring_offset[j] =
2396 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2397 ugeth->p_tx_bd_ring[j] =
2398 (u8 __iomem *) qe_muram_addr(ugeth->
2401 if (!ugeth->p_tx_bd_ring[j]) {
2402 if (netif_msg_ifup(ugeth))
2409 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2421 ugeth->rx_bd_ring_offset[j] =
2423 if (ugeth->rx_bd_ring_offset[j] != 0)
2424 ugeth->p_rx_bd_ring[j] =
2425 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2428 ugeth->rx_bd_ring_offset[j] =
2431 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2432 ugeth->p_rx_bd_ring[j] =
2433 (u8 __iomem *) qe_muram_addr(ugeth->
2436 if (!ugeth->p_rx_bd_ring[j]) {
2437 if (netif_msg_ifup(ugeth))
2448 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2449 ugeth->ug_info->bdRingLenTx[j],
2452 if (ugeth->tx_skbuff[j] == NULL) {
2453 if (netif_msg_ifup(ugeth))
2459 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2460 ugeth->tx_skbuff[j][i] = NULL;
2462 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2463 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2479 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2480 ugeth->ug_info->bdRingLenRx[j],
2483 if (ugeth->rx_skbuff[j] == NULL) {
2484 if (netif_msg_ifup(ugeth))
2490 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2491 ugeth->rx_skbuff[j][i] = NULL;
2493 ugeth->skb_currx[j] = 0;
2494 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2512 ugeth->tx_glbl_pram_offset =
2515 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2516 if (netif_msg_ifup(ugeth))
2522 ugeth->p_tx_glbl_pram =
2523 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2526 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2532 ugeth->thread_dat_tx_offset =
2537 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2538 if (netif_msg_ifup(ugeth))
2545 ugeth->p_thread_data_tx =
2546 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2548 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2552 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2557 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2562 ugeth->send_q_mem_reg_offset =
2566 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2567 if (netif_msg_ifup(ugeth))
2574 ugeth->p_send_q_mem_reg =
2575 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2577 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2583 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2585 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2586 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2587 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2588 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2591 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2593 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2594 (u32) immrbar_virt_to_phys(ugeth->
2596 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2606 ugeth->scheduler_offset =
2609 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2610 if (netif_msg_ifup(ugeth))
2617 ugeth->p_scheduler =
2618 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2620 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2621 ugeth->scheduler_offset);
2623 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2626 out_be32(&ugeth->p_scheduler->mblinterval,
2628 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2630 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2631 out_8(&ugeth->p_scheduler->strictpriorityq,
2633 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2634 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2636 out_8(&ugeth->p_scheduler->weightfactor[i],
2640 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2641 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2642 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2643 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2644 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2645 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2646 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2647 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2654 ugeth->tx_fw_statistics_pram_offset =
2658 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2659 if (netif_msg_ifup(ugeth))
2666 ugeth->p_tx_fw_statistics_pram =
2668 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2670 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2682 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2684 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2691 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2695 ugeth->rx_glbl_pram_offset =
2698 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2699 if (netif_msg_ifup(ugeth))
2705 ugeth->p_rx_glbl_pram =
2706 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2709 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2715 ugeth->thread_dat_rx_offset =
2719 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2720 if (netif_msg_ifup(ugeth))
2727 ugeth->p_thread_data_rx =
2728 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2730 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2733 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2738 ugeth->rx_fw_statistics_pram_offset =
2742 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2743 if (netif_msg_ifup(ugeth))
2749 ugeth->p_rx_fw_statistics_pram =
2751 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2753 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2760 ugeth->rx_irq_coalescing_tbl_offset =
2764 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2765 if (netif_msg_ifup(ugeth))
2772 ugeth->p_rx_irq_coalescing_tbl =
2774 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2775 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2776 ugeth->rx_irq_coalescing_tbl_offset);
2780 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2783 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2790 &ugeth->p_rx_glbl_pram->mrblr);
2792 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2795 &ugeth->p_rx_glbl_pram->minflr,
2796 &ugeth->p_rx_glbl_pram->mrblr);
2798 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2800 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2806 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2813 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2817 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2820 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2823 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2827 ugeth->rx_bd_qs_tbl_offset =
2832 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2833 if (netif_msg_ifup(ugeth))
2840 ugeth->p_rx_bd_qs_tbl =
2841 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2843 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2845 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2853 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2854 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2855 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2856 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2858 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2859 (u32) immrbar_virt_to_phys(ugeth->
2868 if (ugeth->rx_extended_features)
2887 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2897 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2898 ugeth->tx_fw_statistics_pram_offset,
2899 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2900 ugeth->rx_fw_statistics_pram_offset,
2901 &ugeth->p_tx_glbl_pram->temoder,
2902 &ugeth->p_rx_glbl_pram->remoder);
2905 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2910 if (netif_msg_ifup(ugeth))
2918 ugeth->exf_glbl_param_offset =
2921 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2922 if (netif_msg_ifup(ugeth))
2929 ugeth->p_exf_glbl_param =
2930 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2932 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2933 ugeth->exf_glbl_param_offset);
2934 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2942 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2945 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2948 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2950 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2967 if (!(ugeth->p_init_enet_param_shadow =
2969 if (netif_msg_ifup(ugeth))
2976 memset((char *)ugeth->p_init_enet_param_shadow,
2981 ugeth->p_init_enet_param_shadow->resinit1 =
2983 ugeth->p_init_enet_param_shadow->resinit2 =
2985 ugeth->p_init_enet_param_shadow->resinit3 =
2987 ugeth->p_init_enet_param_shadow->resinit4 =
2989 ugeth->p_init_enet_param_shadow->resinit5 =
2991 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2993 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2996 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2997 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3004 if (netif_msg_ifup(ugeth))
3009 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3024 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3030 if (netif_msg_ifup(ugeth))
3036 ugeth->p_init_enet_param_shadow->txglobal =
3037 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3039 fill_init_enet_entries(ugeth,
3040 &(ugeth->p_init_enet_param_shadow->
3045 if (netif_msg_ifup(ugeth))
3053 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3054 if (netif_msg_ifup(ugeth))
3064 if (netif_msg_ifup(ugeth))
3075 ugeth->p_init_enet_param_shadow->resinit1);
3077 ugeth->p_init_enet_param_shadow->resinit2);
3079 ugeth->p_init_enet_param_shadow->resinit3);
3081 ugeth->p_init_enet_param_shadow->resinit4);
3083 ugeth->p_init_enet_param_shadow->resinit5);
3085 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3087 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3090 ugeth->p_init_enet_param_shadow->rxthread[i]);
3092 ugeth->p_init_enet_param_shadow->txglobal);
3095 ugeth->p_init_enet_param_shadow->txthread[i]);
3099 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3113 struct ucc_geth_private *ugeth = netdev_priv(dev);
3124 spin_lock_irqsave(&ugeth->lock, flags);
3129 bd = ugeth->txBd[txQ];
3132 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3135 ugeth->skb_curtx[txQ] =
3136 (ugeth->skb_curtx[txQ] +
3137 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3141 dma_map_single(ugeth->dev, skb->data,
3155 bd = ugeth->p_tx_bd_ring[txQ];
3159 if (bd == ugeth->confBd[txQ]) {
3164 ugeth->txBd[txQ] = bd;
3166 if (ugeth->p_scheduler) {
3167 ugeth->cpucount[txQ]++;
3172 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3176 uccf = ugeth->uccf;
3179 spin_unlock_irqrestore(&ugeth->lock, flags);
3184 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3195 dev = ugeth->ndev;
3198 bd = ugeth->rxBd[rxQ];
3206 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3213 if (netif_msg_rx_err(ugeth))
3220 __skb_queue_head(&ugeth->rx_recycle, skb);
3223 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3233 skb->protocol = eth_type_trans(skb, ugeth->ndev);
3240 skb = get_new_skb(ugeth, bd);
3242 if (netif_msg_rx_err(ugeth))
3248 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3251 ugeth->skb_currx[rxQ] =
3252 (ugeth->skb_currx[rxQ] +
3253 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3256 bd = ugeth->p_rx_bd_ring[rxQ];
3263 ugeth->rxBd[rxQ] = bd;
3270 struct ucc_geth_private *ugeth = netdev_priv(dev);
3274 bd = ugeth->confBd[txQ];
3285 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3291 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3293 ugeth->ug_info->uf_info.max_rx_buf_length +
3295 __skb_queue_head(&ugeth->rx_recycle, skb);
3299 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3300 ugeth->skb_dirtytx[txQ] =
3301 (ugeth->skb_dirtytx[txQ] +
3302 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3312 bd = ugeth->p_tx_bd_ring[txQ];
3315 ugeth->confBd[txQ] = bd;
3321 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3325 ug_info = ugeth->ug_info;
3328 spin_lock(&ugeth->lock);
3330 ucc_geth_tx(ugeth->ndev, i);
3331 spin_unlock(&ugeth->lock);
3335 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3339 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3348 struct ucc_geth_private *ugeth = netdev_priv(dev);
3356 uccf = ugeth->uccf;
3357 ug_info = ugeth->ug_info;
3367 if (napi_schedule_prep(&ugeth->napi)) {
3370 __napi_schedule(&ugeth->napi);
3393 struct ucc_geth_private *ugeth = netdev_priv(dev);
3394 int irq = ugeth->ug_info->uf_info.irq;
3404 struct ucc_geth_private *ugeth = netdev_priv(dev);
3419 spin_lock_irq(&ugeth->lock);
3426 &ugeth->ug_regs->macstnaddr1,
3427 &ugeth->ug_regs->macstnaddr2);
3428 spin_unlock_irq(&ugeth->lock);
3433 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3435 struct net_device *dev = ugeth->ndev;
3438 err = ucc_struct_init(ugeth);
3440 if (netif_msg_ifup(ugeth))
3446 err = ucc_geth_startup(ugeth);
3448 if (netif_msg_ifup(ugeth))
3454 err = adjust_enet_interface(ugeth);
3456 if (netif_msg_ifup(ugeth))
3470 &ugeth->ug_regs->macstnaddr1,
3471 &ugeth->ug_regs->macstnaddr2);
3473 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3475 if (netif_msg_ifup(ugeth))
3482 ucc_geth_stop(ugeth);
3490 struct ucc_geth_private *ugeth = netdev_priv(dev);
3497 if (netif_msg_ifup(ugeth))
3506 if (netif_msg_ifup(ugeth))
3512 err = ucc_geth_init_mac(ugeth);
3514 if (netif_msg_ifup(ugeth))
3520 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3523 if (netif_msg_ifup(ugeth))
3529 phy_start(ugeth->phydev);
3530 napi_enable(&ugeth->napi);
3534 qe_alive_during_sleep() || ugeth->phydev->irq);
3535 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3540 ucc_geth_stop(ugeth);
3547 struct ucc_geth_private *ugeth = netdev_priv(dev);
3551 napi_disable(&ugeth->napi);
3553 ucc_geth_stop(ugeth);
3555 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3565 struct ucc_geth_private *ugeth;
3568 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3569 dev = ugeth->ndev;
3575 ugeth_dump_regs(ugeth);
3595 struct ucc_geth_private *ugeth = netdev_priv(dev);
3598 schedule_work(&ugeth->timeout_work);
3607 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3613 napi_disable(&ugeth->napi);
3619 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3621 if (ugeth->wol_en & WAKE_MAGIC) {
3622 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3623 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3624 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3625 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3626 phy_stop(ugeth->phydev);
3635 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3642 if (ugeth->wol_en & WAKE_MAGIC) {
3643 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3644 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3645 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3647 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3653 ucc_geth_memclean(ugeth);
3655 err = ucc_geth_init_mac(ugeth);
3663 ugeth->oldlink = 0;
3664 ugeth->oldspeed = 0;
3665 ugeth->oldduplex = -1;
3667 phy_stop(ugeth->phydev);
3668 phy_start(ugeth->phydev);
3670 napi_enable(&ugeth->napi);
3709 struct ucc_geth_private *ugeth = netdev_priv(dev);
3714 if (!ugeth->phydev)
3717 return phy_mii_ioctl(ugeth->phydev, rq, cmd);
3740 struct ucc_geth_private *ugeth = NULL;
3905 dev = alloc_etherdev(sizeof(*ugeth));
3910 ugeth = netdev_priv(dev);
3911 spin_lock_init(&ugeth->lock);
3914 INIT_LIST_HEAD(&ugeth->group_hash_q);
3915 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3928 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3929 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3932 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3933 ugeth->phy_interface = phy_interface;
3934 ugeth->max_speed = max_speed;
3938 if (netif_msg_probe(ugeth))
3949 ugeth->ug_info = ug_info;
3950 ugeth->dev = device;
3951 ugeth->ndev = dev;
3952 ugeth->node = np;
3961 struct ucc_geth_private *ugeth = netdev_priv(dev);
3965 ucc_geth_memclean(ugeth);