Lines Matching defs:olympic_mmio
245 olympic_priv->olympic_mmio = ioremap(pci_resource_start(pdev,1),256);
247 if (!olympic_priv->olympic_mmio || !olympic_priv->olympic_lap) {
281 if (olympic_priv->olympic_mmio)
282 iounmap(olympic_priv->olympic_mmio);
298 u8 __iomem *olympic_mmio, *init_srb,*adapter_addr;
303 olympic_mmio=olympic_priv->olympic_mmio;
306 printk("%s. I/O at %hx, MMIO at %p, LAP at %p, using irq %d\n", olympic_priv->olympic_card_name, (unsigned int) dev->base_addr,olympic_priv->olympic_mmio, olympic_priv->olympic_lap, dev->irq);
308 writel(readl(olympic_mmio+BCTL) | BCTL_SOFTRESET,olympic_mmio+BCTL);
310 while((readl(olympic_mmio+BCTL)) & BCTL_SOFTRESET) {
320 if(!(readl(olympic_mmio+BCTL) & BCTL_MODE_INDICATOR)) {
321 writel(readl(olympic_priv->olympic_mmio+FERMASK)|FERMASK_INT_BIT, olympic_mmio+FERMASK);
325 printk("BCTL: %x\n",readl(olympic_mmio+BCTL));
326 printk("GPR: %x\n",readw(olympic_mmio+GPR));
327 printk("SISRMASK: %x\n",readl(olympic_mmio+SISR_MASK));
333 writel(readl(olympic_mmio+BCTL)|BCTL_MIMREB,olympic_mmio+BCTL);
336 writew(readw(olympic_mmio+GPR)|GPR_AUTOSENSE,olympic_mmio+GPR);
342 writew(GPR_16MBPS, olympic_mmio+GPR);
346 writew(0, olympic_mmio+GPR);
349 writew(readw(olympic_mmio+GPR)|GPR_NEPTUNE_BF,olympic_mmio+GPR);
352 printk("GPR = %x\n",readw(olympic_mmio + GPR) ) ;
360 if(!(readl(olympic_mmio+BCTL) & BCTL_MODE_INDICATOR)) {
362 while (!(readl(olympic_mmio+CLKCTL) & CLKCTL_PAUSE)) {
369 writel(readl(olympic_mmio+CLKCTL) & ~CLKCTL_PAUSE, olympic_mmio+CLKCTL) ;
373 writel((1<<15),olympic_mmio+SISR_MASK_SUM);
376 while(!((readl(olympic_mmio+SISR_RR)) & SISR_SRB_REPLY)) {
384 writel(readw(olympic_mmio+LAPWWO),olympic_mmio+LAPA);
387 printk("LAPWWO: %x, LAPA: %x\n",readl(olympic_mmio+LAPWWO), readl(olympic_mmio+LAPA));
390 init_srb=olympic_priv->olympic_lap + ((readw(olympic_mmio+LAPWWO)) & (~0xf800));
420 writel(uaa_addr,olympic_mmio+LAPA);
439 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio,*init_srb;
453 printk("BMCTL: %x\n",readl(olympic_mmio+BMCTL_SUM));
454 printk("pending ints: %x\n",readl(olympic_mmio+SISR_RR));
457 writel(SISR_MI,olympic_mmio+SISR_MASK_SUM);
459 writel(SISR_MI | SISR_SRB_REPLY, olympic_mmio+SISR_MASK); /* more ints later, doesn't stop arb cmd interrupt */
461 writel(LISR_LIE,olympic_mmio+LISR); /* more ints later */
465 writel(readw(olympic_mmio+LAPWWO),olympic_mmio+LAPA);
466 init_srb=olympic_priv->olympic_lap + ((readw(olympic_mmio+LAPWWO)) & (~0xf800));
469 printk("LAPWWO: %x, LAPA: %x\n",readw(olympic_mmio+LAPWWO), readl(olympic_mmio+LAPA));
470 printk("SISR Mask = %04x\n", readl(olympic_mmio+SISR_MASK));
503 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
517 readl(olympic_mmio+SISR),
518 readl(olympic_mmio+LISR));
605 writel((3<<16),olympic_mmio+BMCTL_RWM); /* Ensure end of frame generated interrupts */
607 writel(BMCTL_RX_DIS|3,olympic_mmio+BMCTL_RWM); /* Yes, this the enables RX channel */
632 writel(olympic_priv->rx_ring_dma_addr, olympic_mmio+RXDESCQ);
633 writel(olympic_priv->rx_ring_dma_addr, olympic_mmio+RXCDA);
634 writew(i, olympic_mmio+RXDESCQCNT);
638 writel(olympic_priv->rx_status_ring_dma_addr, olympic_mmio+RXSTATQ);
639 writel(olympic_priv->rx_status_ring_dma_addr, olympic_mmio+RXCSA);
644 writew(i, olympic_mmio+RXSTATQCNT);
647 printk("# of rx buffers: %d, RXENQ: %x\n",i, readw(olympic_mmio+RXENQ));
648 printk("RXCSA: %x, rx_status_ring[0]: %p\n",readl(olympic_mmio+RXCSA),&olympic_priv->olympic_rx_status_ring[0]);
653 printk("RXCDA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCDA),&olympic_priv->olympic_rx_ring[0]);
658 writew((((readw(olympic_mmio+RXENQ)) & 0x8000) ^ 0x8000) | i,olympic_mmio+RXENQ);
661 printk("# of rx buffers: %d, RXENQ: %x\n",i, readw(olympic_mmio+RXENQ));
662 printk("RXCSA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCSA),&olympic_priv->olympic_rx_status_ring[0]);
663 printk("RXCDA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCDA),&olympic_priv->olympic_rx_ring[0]);
666 writel(SISR_RX_STATUS | SISR_RX_NOBUF,olympic_mmio+SISR_MASK_SUM);
670 writel(BMCTL_TX1_DIS,olympic_mmio+BMCTL_RWM); /* Yes, this enables TX channel 1 */
677 writel(olympic_priv->tx_ring_dma_addr, olympic_mmio+TXDESCQ_1);
678 writel(olympic_priv->tx_ring_dma_addr, olympic_mmio+TXCDA_1);
679 writew(OLYMPIC_TX_RING_SIZE, olympic_mmio+TXDESCQCNT_1);
683 writel(olympic_priv->tx_status_ring_dma_addr,olympic_mmio+TXSTATQ_1);
684 writel(olympic_priv->tx_status_ring_dma_addr,olympic_mmio+TXCSA_1);
685 writew(OLYMPIC_TX_RING_SIZE,olympic_mmio+TXSTATQCNT_1);
690 writel(0xffffffff, olympic_mmio+EISR_RWM) ; /* clean the eisr */
691 writel(0,olympic_mmio+EISR) ;
692 writel(EISR_MASK_OPTIONS,olympic_mmio+EISR_MASK) ; /* enables most of the TX error interrupts */
693 writel(SISR_TX1_EOF | SISR_ADAPTER_CHECK | SISR_ARB_CMD | SISR_TRB_REPLY | SISR_ASB_FREE | SISR_ERR,olympic_mmio+SISR_MASK_SUM);
696 printk("BMCTL: %x\n",readl(olympic_mmio+BMCTL_SUM));
697 printk("SISR MASK: %x\n",readl(olympic_mmio+SISR_MASK));
747 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
880 writew((((readw(olympic_mmio+RXENQ)) & 0x8000) ^ 0x8000) | buffer_cnt , olympic_mmio+RXENQ);
921 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
930 sisr=readl(olympic_mmio+SISR) ;
933 sisr=readl(olympic_mmio+SISR_RR) ; /* Read & Reset sisr */
949 if((sisr & SISR_ERR) && (readl(olympic_mmio+EISR) & EISR_MASK_OPTIONS)) {
950 printk(KERN_ERR "Olympic: EISR Error, EISR=%08x\n",readl(olympic_mmio+EISR)) ;
994 writel(readl(olympic_mmio+LAPWWC),olympic_mmio+LAPA);
995 adapter_check_area = olympic_priv->olympic_lap + ((readl(olympic_mmio+LAPWWC)) & (~0xf800)) ;
1026 printk(KERN_WARNING "%s: SISR_MASK: %x\n",dev->name, readl(olympic_mmio+SISR_MASK)) ;
1028 writel(SISR_MI,olympic_mmio+SISR_MASK_SUM);
1038 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
1054 writew((((readw(olympic_mmio+TXENQ_1)) & 0x8000) ^ 0x8000) | 1,olympic_mmio+TXENQ_1);
1069 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio,*srb;
1076 writel(olympic_priv->srb,olympic_mmio+LAPA);
1089 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1098 printk(KERN_WARNING "SISR=%x MISR=%x\n",readl(olympic_mmio+SISR),readl(olympic_mmio+LISR));
1117 writel(readl(olympic_mmio+BCTL)|(3<<13),olympic_mmio+BCTL);
1119 writel(readl(olympic_mmio+BCTL)&~(3<<13),olympic_mmio+BCTL);
1139 u8 __iomem *olympic_mmio = olympic_priv->olympic_mmio ;
1145 writel(olympic_priv->srb,olympic_mmio+LAPA);
1169 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1199 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1206 u8 __iomem *olympic_mmio = olympic_priv->olympic_mmio ;
1209 writel(olympic_priv->srb,olympic_mmio+LAPA);
1373 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
1442 writel(LISR_ARB_FREE,olympic_priv->olympic_mmio + LISR_SUM);
1448 writel(LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1458 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1469 writel(LISR_ARB_FREE,olympic_priv->olympic_mmio+LISR_SUM);
1487 writel(readl(olympic_mmio+BCTL)|(3<<13),olympic_mmio+BCTL);
1489 writel(readl(olympic_mmio+BCTL)&~(3<<13),olympic_mmio+BCTL);
1528 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1546 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1572 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1723 iounmap(olympic_priv->olympic_mmio) ;