• Home
  • History
  • Annotate
  • Raw
  • Download
  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/ixgbe/

Lines Matching refs:_i

107 #define IXGBE_EICS_EX(_i)   (0x00A90 + (_i) * 4)
108 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
109 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
110 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
120 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
121 (0x012300 + (((_i) - 24) * 4)))
125 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
130 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
138 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
139 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
141 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
142 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
143 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
149 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
150 (0x0D000 + ((_i - 64) * 0x40)))
151 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
152 (0x0D004 + ((_i - 64) * 0x40)))
153 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
154 (0x0D008 + ((_i - 64) * 0x40)))
155 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
156 (0x0D010 + ((_i - 64) * 0x40)))
157 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
158 (0x0D018 + ((_i - 64) * 0x40)))
159 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
160 (0x0D028 + ((_i - 64) * 0x40)))
170 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
171 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
172 (0x0D014 + ((_i - 64) * 0x40))))
179 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
180 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
181 (0x0D00C + ((_i - 64) * 0x40))))
183 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
195 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
196 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
197 (0x0A200 + ((_i) * 8)))
198 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
199 (0x0A204 + ((_i) * 8)))
200 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
201 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
203 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
204 (0x0EA00 + ((_i) * 4)))
206 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
208 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
213 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
214 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
215 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
216 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
217 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
218 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
222 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
223 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
224 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
226 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
227 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
229 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
230 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
231 #define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
232 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
233 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
234 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
236 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
237 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
240 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
241 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
263 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
272 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
273 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
274 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
275 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
276 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
277 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
278 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
279 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
288 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
296 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
298 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
300 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
382 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
383 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
384 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
385 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
386 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
387 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
427 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
428 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
477 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
479 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
482 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
489 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
490 (0x0D02C + ((_i - 64) * 0x40)))
510 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
511 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
512 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
513 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
514 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
515 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
529 #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
575 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
585 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
595 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
596 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
597 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
598 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
599 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
600 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
601 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
616 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
639 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
640 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
641 (0x08600 + ((_i) * 4)))
642 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
644 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
645 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
646 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
647 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
648 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
649 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
650 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
660 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
661 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
665 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
667 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
668 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
670 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
671 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
765 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
767 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
772 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
776 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
777 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
789 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
796 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
797 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
798 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
799 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
800 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
801 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
802 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
803 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
876 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1267 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1268 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1274 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1347 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1348 #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1349 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1350 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1351 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1882 #define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
1883 #define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
1884 #define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))