Lines Matching refs:WriteReg
244 static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)
268 WriteReg(BaseAddr, RegNum, Wtemp);
292 WriteReg(iobase, I_CF_L_2, low);
293 WriteReg(iobase, I_CF_H_2, high);
341 #define SetSIRBOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_BOF,val)
342 #define SetSIREOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_EOF,val)
395 #define SetPacketAddr(BaseAddr,addr) WriteReg(BaseAddr,P_ADDR,addr)
415 WriteReg(iobase, TIMER, count);
427 WriteReg(iobase, TX_C_L, low);
428 WriteReg(iobase, TX_C_H, high);
437 WriteReg(iobase, RESET, type);
539 WriteReg(iobase, 0x34, bTmp | Clk_bit);
541 WriteReg(iobase, 0x34, bTmp & ~Clk_bit);
555 WriteReg(iobase, 0x34, bTmp);
563 WriteReg(iobase, 0x34, bTmp);
699 WriteReg(iobase, 0x35, bTmp | 0x40); // Driver ITMOFF
700 WriteReg(iobase, 0x28, bTmp | 0x80); // enable All interrupt
721 WriteReg(iobase, I_ST_CT_0, 0x00); // open CHIP on
747 WriteReg(iobase, I_ST_CT_0, 0x80);
785 WriteReg(iobase, I_CF_H_1, temp);
798 WriteReg(iobase, I_CF_L_1, temp);
799 WriteReg(iobase, I_CF_H_1, temp1);
808 WriteReg(iobase, I_CF_L_1, temp);
817 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
827 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
837 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
847 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);