Lines Matching defs:iobase
286 static void SetMaxRxPacketSize(__u16 iobase, __u16 size)
292 WriteReg(iobase, I_CF_L_2, low);
293 WriteReg(iobase, I_CF_H_2, high);
301 static void SetFIFO(__u16 iobase, __u16 value)
305 WriteRegBit(iobase, 0x11, 0, 0);
306 WriteRegBit(iobase, 0x11, 7, 1);
309 WriteRegBit(iobase, 0x11, 0, 0);
310 WriteRegBit(iobase, 0x11, 7, 0);
313 WriteRegBit(iobase, 0x11, 0, 1);
314 WriteRegBit(iobase, 0x11, 7, 0);
317 WriteRegBit(iobase, 0x11, 0, 0);
318 WriteRegBit(iobase, 0x11, 7, 0);
412 static void SetTimer(__u16 iobase, __u8 count)
414 EnTimerInt(iobase, OFF);
415 WriteReg(iobase, TIMER, count);
416 EnTimerInt(iobase, ON);
420 static void SetSendByte(__u16 iobase, __u32 count)
427 WriteReg(iobase, TX_C_L, low);
428 WriteReg(iobase, TX_C_H, high);
432 static void ResetChip(__u16 iobase, __u8 type)
437 WriteReg(iobase, RESET, type);
440 static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self)
445 low = ReadReg(iobase, RX_C_L);
446 high = ReadReg(iobase, RX_C_H);
450 low = ReadReg(iobase, RX_C_L);
451 high = ReadReg(iobase, RX_C_H);
461 static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self)
466 low = ReadReg(iobase, RX_P_L);
467 high = ReadReg(iobase, RX_P_H);
477 static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self)
482 low = ReadReg(iobase, RX_P_L);
483 high = ReadReg(iobase, RX_P_H);
495 low=ReadReg(iobase,RX_C_L);
496 high=ReadReg(iobase,RX_C_H);
534 static void ActClk(__u16 iobase, __u8 value)
537 bTmp = ReadReg(iobase, 0x34);
539 WriteReg(iobase, 0x34, bTmp | Clk_bit);
541 WriteReg(iobase, 0x34, bTmp & ~Clk_bit);
544 static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx)
548 bTmp = ReadReg(iobase, 0x34);
555 WriteReg(iobase, 0x34, bTmp);
563 WriteReg(iobase, 0x34, bTmp);
566 static void Wr_Byte(__u16 iobase, __u8 data)
572 ClkTx(iobase, 0, 1);
575 ActClk(iobase, 1);
581 ClkTx(iobase, 0, 1); //bit data = 1;
583 ClkTx(iobase, 0, 0); //bit data = 1;
587 ActClk(iobase, 1); //clk hi
592 static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index)
598 ClkTx(iobase, 0, 0);
600 ActClk(iobase, 1);
602 Wr_Byte(iobase, bTmp);
604 ClkTx(iobase, 0, 0);
607 ActClk(iobase, 1);
609 ActClk(iobase, 0);
611 ClkTx(iobase, 0, 1);
613 bTmp = ReadReg(iobase, 0x34);
619 ActClk(iobase, 1);
621 ActClk(iobase, 0);
622 bTmp = ReadReg(iobase, 0x34);
632 ActClk(iobase, 1);
634 ActClk(iobase, 0);
637 bTmp = ReadReg(iobase, 0x34);
640 ActClk(iobase, 1);
642 ActClk(iobase, 0);
645 ClkTx(iobase, 0, 0);
648 ActClk(iobase, 1);
650 ActClk(iobase, 0);
656 static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data)
661 ClkTx(iobase, 0, 0);
663 ActClk(iobase, 1);
666 Wr_Byte(iobase, bTmp);
667 Wr_Byte(iobase, data);
669 ClkTx(iobase, 0, 0);
671 ActClk(iobase, 1);
674 ActClk(iobase, 0);
677 static void ResetDongle(__u16 iobase)
680 ClkTx(iobase, 0, 0);
683 ActClk(iobase, 1);
685 ActClk(iobase, 0);
688 ActClk(iobase, 0);
691 static void SetSITmode(__u16 iobase)
698 bTmp = ReadReg(iobase, 0x35);
699 WriteReg(iobase, 0x35, bTmp | 0x40); // Driver ITMOFF
700 WriteReg(iobase, 0x28, bTmp | 0x80); // enable All interrupt
703 static void SI_SetMode(__u16 iobase, int mode)
709 SetSITmode(iobase);
710 ResetDongle(iobase);
712 Wr_Indx(iobase, 0x40, 0x0, 0x17); //RX ,APEN enable,Normal power
713 Wr_Indx(iobase, 0x40, 0x1, mode); //Set Mode
714 Wr_Indx(iobase, 0x40, 0x2, 0xff); //Set power to FIR VFIR > 1m
715 bTmp = Rd_Indx(iobase, 0x40, 1);
718 static void InitCard(__u16 iobase)
720 ResetChip(iobase, 5);
721 WriteReg(iobase, I_ST_CT_0, 0x00); // open CHIP on
722 SetSIRBOF(iobase, 0xc0); // hardware default value
723 SetSIREOF(iobase, 0xc1);
726 static void CommonInit(__u16 iobase)
728 // EnTXCRC(iobase,0);
729 SwapDMA(iobase, OFF);
730 SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
731 EnRXFIFOReadyInt(iobase, OFF);
732 EnRXFIFOHalfLevelInt(iobase, OFF);
733 EnTXFIFOHalfLevelInt(iobase, OFF);
734 EnTXFIFOUnderrunEOMInt(iobase, ON);
735 // EnTXFIFOReadyInt(iobase,ON);
736 InvertTX(iobase, OFF);
737 InvertRX(iobase, OFF);
739 if (IsSIROn(iobase)) {
740 SIRFilter(iobase, ON);
741 SIRRecvAny(iobase, ON);
743 SIRFilter(iobase, OFF);
744 SIRRecvAny(iobase, OFF);
746 EnRXSpecInt(iobase, ON);
747 WriteReg(iobase, I_ST_CT_0, 0x80);
748 EnableDMA(iobase, ON);
751 static void SetBaudRate(__u16 iobase, __u32 rate)
755 if (IsSIROn(iobase)) {
778 } else if (IsMIROn(iobase)) {
780 } else if (IsFIROn(iobase)) {
783 temp = (ReadReg(iobase, I_CF_H_1) & 0x03);
785 WriteReg(iobase, I_CF_H_1, temp);
788 static void SetPulseWidth(__u16 iobase, __u8 width)
792 temp = (ReadReg(iobase, I_CF_L_1) & 0x1f);
793 temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc);
798 WriteReg(iobase, I_CF_L_1, temp);
799 WriteReg(iobase, I_CF_H_1, temp1);
802 static void SetSendPreambleCount(__u16 iobase, __u8 count)
806 temp = ReadReg(iobase, I_CF_L_1) & 0xe0;
808 WriteReg(iobase, I_CF_L_1, temp);