Lines Matching defs:iobase
209 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
359 static inline void register_bank(int iobase, int bank)
361 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
362 iobase + IRCC_MASTER);
758 int iobase = self->io.fir_base;
760 register_bank(iobase, 0);
761 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
762 outb(0x00, iobase + IRCC_MASTER);
764 register_bank(iobase, 1);
765 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
766 iobase + IRCC_SCE_CFGA);
769 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
770 iobase + IRCC_SCE_CFGB);
772 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
773 iobase + IRCC_SCE_CFGB);
775 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
776 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
778 register_bank(iobase, 4);
779 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
781 register_bank(iobase, 0);
782 outb(0, iobase + IRCC_LCR_A);
787 outb(0x00, iobase + IRCC_MASTER);
1106 int iobase;
1114 iobase = self->io.sir_base;
1120 outb(0, iobase + UART_IER);
1137 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1138 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1139 outb(divisor >> 8, iobase + UART_DLM);
1140 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1141 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1144 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1227 int iobase = self->io.fir_base;
1232 register_bank(iobase, 0);
1233 outb(0x00, iobase + IRCC_LCR_B);
1234 register_bank(iobase, 1);
1235 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1236 iobase + IRCC_SCE_CFGB);
1241 register_bank(iobase, 4);
1242 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1243 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1244 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1247 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1248 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1253 register_bank(iobase, 1);
1254 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1255 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1263 register_bank(iobase, 0);
1264 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1265 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1268 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1280 int iobase = self->io.fir_base;
1283 register_bank(iobase, 1);
1284 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1285 iobase + IRCC_SCE_CFGB);
1288 register_bank(iobase, 0);
1289 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1294 register_bank(iobase, 0);
1295 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1296 outb(0x00, iobase + IRCC_MASTER);
1320 int iobase = self->io.fir_base;
1323 register_bank(iobase, 0);
1324 outb(0x00, iobase + IRCC_LCR_B);
1327 register_bank(iobase, 1);
1328 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1329 iobase + IRCC_SCE_CFGB);
1335 register_bank(iobase, 4);
1336 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1337 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1344 register_bank(iobase, 1);
1345 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1346 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1349 register_bank(iobase, 0);
1350 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1351 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1354 register_bank(iobase, 0);
1356 iobase + IRCC_LCR_B);
1371 int iobase = self->io.fir_base;
1373 register_bank(iobase, 0);
1376 register_bank(iobase, 0);
1377 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1378 lsr= inb(iobase + IRCC_LSR);
1379 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1437 int iobase;
1441 iobase = self->io.sir_base;
1449 inb(iobase + UART_RX));
1456 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1470 int iobase, iir, lcra, lsr;
1482 iobase = self->io.fir_base;
1484 register_bank(iobase, 0);
1485 iir = inb(iobase + IRCC_IIR);
1491 outb(0, iobase + IRCC_IER);
1492 lcra = inb(iobase + IRCC_LCR_A);
1493 lsr = inb(iobase + IRCC_LSR);
1512 register_bank(iobase, 0);
1513 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1530 int iobase;
1536 iobase = self->io.sir_base;
1538 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1543 lsr = inb(iobase + UART_LSR);
1545 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1546 __func__, iir, lsr, iobase);
1571 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1606 int iobase = self->io.fir_base;
1611 register_bank(iobase, 0);
1612 outb(0, iobase + IRCC_IER);
1613 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1614 outb(0x00, iobase + IRCC_MASTER);
1868 int iobase;
1871 iobase = self->io.sir_base;
1874 outb(0, iobase + UART_MCR);
1877 outb(0, iobase + UART_IER);
1891 int iobase;
1898 iobase = self->io.sir_base;
1903 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1937 outb(fcr, iobase + UART_FCR);
1940 outb(UART_IER_RDI, iobase + UART_IER);
1946 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1951 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1956 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1964 outb(buf[actual], iobase + UART_TX);
2049 int iobase = self->io.sir_base;
2053 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2134 /* FIR iobase */
2177 /* SIR iobase */
2459 unsigned short iobase = conf->cfg_base;
2462 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2463 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2464 tmpbyte = inb(iobase +1); // Read device ID
2470 outb(0x24, iobase); // select CR24 - UART1 base addr
2471 outb(0x00, iobase + 1); // disable UART1
2472 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2473 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2474 tmpbyte = inb(iobase + 1);
2482 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2483 tmpbyte = inb(iobase + 1);
2486 outb(tmpbyte, iobase + 1);
2487 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2494 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2495 outb((conf->fir_io >> 3), iobase + 1);
2496 tmpbyte = inb(iobase + 1);
2503 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2504 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2505 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2511 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2512 tmpbyte = inb(iobase + 1);
2515 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2517 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2518 tmpbyte = inb(iobase + 1);
2519 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2522 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2523 tmpbyte = inb(iobase + 1);
2524 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2526 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2527 tmpbyte = inb(iobase + 1);
2528 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2530 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2531 tmpbyte = inb(iobase + 1);
2532 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2534 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration