Lines Matching refs:mal
2 * drivers/net/ibm_newemac/mal.c
36 int __devinit mal_register_commac(struct mal_instance *mal,
41 spin_lock_irqsave(&mal->lock, flags);
43 MAL_DBG(mal, "reg(%08x, %08x)" NL,
47 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
48 (mal->rx_chan_mask & commac->rx_chan_mask)) {
49 spin_unlock_irqrestore(&mal->lock, flags);
50 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
51 mal->index);
55 if (list_empty(&mal->list))
56 napi_enable(&mal->napi);
57 mal->tx_chan_mask |= commac->tx_chan_mask;
58 mal->rx_chan_mask |= commac->rx_chan_mask;
59 list_add(&commac->list, &mal->list);
61 spin_unlock_irqrestore(&mal->lock, flags);
66 void mal_unregister_commac(struct mal_instance *mal,
71 spin_lock_irqsave(&mal->lock, flags);
73 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
76 mal->tx_chan_mask &= ~commac->tx_chan_mask;
77 mal->rx_chan_mask &= ~commac->rx_chan_mask;
79 if (list_empty(&mal->list))
80 napi_disable(&mal->napi);
82 spin_unlock_irqrestore(&mal->lock, flags);
85 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
87 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
90 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
94 "mal%d: incorrect RX size %lu for the channel %d\n",
95 mal->index, size, channel);
99 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
103 int mal_tx_bd_offset(struct mal_instance *mal, int channel)
105 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
110 int mal_rx_bd_offset(struct mal_instance *mal, int channel)
112 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
113 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
116 void mal_enable_tx_channel(struct mal_instance *mal, int channel)
120 spin_lock_irqsave(&mal->lock, flags);
122 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
124 set_mal_dcrn(mal, MAL_TXCASR,
125 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
127 spin_unlock_irqrestore(&mal->lock, flags);
130 void mal_disable_tx_channel(struct mal_instance *mal, int channel)
132 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
134 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
137 void mal_enable_rx_channel(struct mal_instance *mal, int channel)
149 spin_lock_irqsave(&mal->lock, flags);
151 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
153 set_mal_dcrn(mal, MAL_RXCASR,
154 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
156 spin_unlock_irqrestore(&mal->lock, flags);
159 void mal_disable_rx_channel(struct mal_instance *mal, int channel)
169 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
171 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
174 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
178 spin_lock_irqsave(&mal->lock, flags);
180 MAL_DBG(mal, "poll_add(%p)" NL, commac);
185 list_add_tail(&commac->poll_list, &mal->poll_list);
187 spin_unlock_irqrestore(&mal->lock, flags);
190 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
194 spin_lock_irqsave(&mal->lock, flags);
196 MAL_DBG(mal, "poll_del(%p)" NL, commac);
200 spin_unlock_irqrestore(&mal->lock, flags);
204 static inline void mal_enable_eob_irq(struct mal_instance *mal)
206 MAL_DBG2(mal, "enable_irq" NL);
208 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
212 static inline void mal_disable_eob_irq(struct mal_instance *mal)
214 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
216 MAL_DBG2(mal, "disable_irq" NL);
221 struct mal_instance *mal = dev_instance;
223 u32 esr = get_mal_dcrn(mal, MAL_ESR);
226 set_mal_dcrn(mal, MAL_ESR, esr);
228 MAL_DBG(mal, "SERR %08x" NL, esr);
244 "mal%d: system error, "
246 mal->index, esr);
255 "mal%d: system error, OPB (ESR = 0x%08x)\n",
256 mal->index, esr);
261 static inline void mal_schedule_poll(struct mal_instance *mal)
263 if (likely(napi_schedule_prep(&mal->napi))) {
264 MAL_DBG2(mal, "schedule_poll" NL);
265 mal_disable_eob_irq(mal);
266 __napi_schedule(&mal->napi);
268 MAL_DBG2(mal, "already in poll" NL);
273 struct mal_instance *mal = dev_instance;
275 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
277 MAL_DBG2(mal, "txeob %08x" NL, r);
279 mal_schedule_poll(mal);
280 set_mal_dcrn(mal, MAL_TXEOBISR, r);
283 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
293 struct mal_instance *mal = dev_instance;
295 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
297 MAL_DBG2(mal, "rxeob %08x" NL, r);
299 mal_schedule_poll(mal);
300 set_mal_dcrn(mal, MAL_RXEOBISR, r);
303 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
313 struct mal_instance *mal = dev_instance;
315 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
316 set_mal_dcrn(mal, MAL_TXDEIR, deir);
318 MAL_DBG(mal, "txde %08x" NL, deir);
322 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
323 mal->index, deir);
330 struct mal_instance *mal = dev_instance;
333 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
335 MAL_DBG(mal, "rxde %08x" NL, deir);
337 list_for_each(l, &mal->list) {
345 mal_schedule_poll(mal);
346 set_mal_dcrn(mal, MAL_RXDEIR, deir);
353 struct mal_instance *mal = dev_instance;
354 u32 esr = get_mal_dcrn(mal, MAL_ESR);
370 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
377 napi_synchronize(&mal->napi);
380 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
390 napi_schedule(&mal->napi);
395 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
400 MAL_DBG2(mal, "poll(%d)" NL, budget);
403 list_for_each(l, &mal->poll_list) {
414 list_for_each(l, &mal->poll_list) {
430 spin_lock_irqsave(&mal->lock, flags);
432 mal_enable_eob_irq(mal);
433 spin_unlock_irqrestore(&mal->lock, flags);
436 list_for_each(l, &mal->poll_list) {
443 MAL_DBG2(mal, "rotting packet" NL);
445 mal_disable_eob_irq(mal);
447 MAL_DBG2(mal, "already in poll list" NL);
458 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
462 static void mal_reset(struct mal_instance *mal)
466 MAL_DBG(mal, "reset" NL);
468 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
471 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
475 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
478 int mal_get_regs_len(struct mal_instance *mal)
484 void *mal_dump_regs(struct mal_instance *mal, void *buf)
490 hdr->version = mal->version;
491 hdr->index = mal->index;
493 regs->tx_count = mal->num_tx_chans;
494 regs->rx_count = mal->num_rx_chans;
496 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
497 regs->esr = get_mal_dcrn(mal, MAL_ESR);
498 regs->ier = get_mal_dcrn(mal, MAL_IER);
499 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
500 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
501 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
502 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
503 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
504 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
505 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
506 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
509 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
512 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
513 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
521 struct mal_instance *mal;
530 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
531 if (!mal) {
533 "mal%d: out of memory allocating MAL structure!\n",
537 mal->index = index;
538 mal->ofdev = ofdev;
539 mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1;
541 MAL_DBG(mal, "probe" NL);
546 "mal%d: can't find MAL num-tx-chans property!\n",
551 mal->num_tx_chans = prop[0];
556 "mal%d: can't find MAL num-rx-chans property!\n",
561 mal->num_rx_chans = prop[0];
566 "mal%d: can't find DCR resource!\n", index);
570 mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100);
571 if (!DCR_MAP_OK(mal->dcr_host)) {
573 "mal%d: failed to map DCRs !\n", index);
581 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT |
591 mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
592 mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
593 mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2);
595 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
596 mal->txde_irq = mal->rxde_irq = mal->serr_irq;
598 mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3);
599 mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4);
602 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||
603 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||
604 mal->rxde_irq == NO_IRQ) {
606 "mal%d: failed to map interrupts !\n", index);
611 INIT_LIST_HEAD(&mal->poll_list);
612 INIT_LIST_HEAD(&mal->list);
613 spin_lock_init(&mal->lock);
615 init_dummy_netdev(&mal->dummy_dev);
617 netif_napi_add(&mal->dummy_dev, &mal->napi, mal_poll,
621 mal_reset(mal);
624 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
634 set_mal_dcrn(mal, MAL_CFG, cfg);
637 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
638 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
641 (NUM_TX_BUFF * mal->num_tx_chans +
642 NUM_RX_BUFF * mal->num_rx_chans);
643 mal->bd_virt =
644 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
646 if (mal->bd_virt == NULL) {
648 "mal%d: out of memory allocating RX/TX descriptors!\n",
653 memset(mal->bd_virt, 0, bd_size);
655 for (i = 0; i < mal->num_tx_chans; ++i)
656 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
658 mal_tx_bd_offset(mal, i));
660 for (i = 0; i < mal->num_rx_chans; ++i)
661 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
663 mal_rx_bd_offset(mal, i));
665 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
675 err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal);
678 err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal);
681 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
684 err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal);
687 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
692 if (mal->version == 2)
693 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS);
695 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS);
698 mal_enable_eob_irq(mal);
702 mal->version, ofdev->dev.of_node->full_name,
703 mal->num_tx_chans, mal->num_rx_chans);
707 dev_set_drvdata(&ofdev->dev, mal);
709 mal_dbg_register(mal);
714 free_irq(mal->rxde_irq, mal);
716 free_irq(mal->txeob_irq, mal);
718 free_irq(mal->txde_irq, mal);
720 free_irq(mal->serr_irq, mal);
722 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
724 dcr_unmap(mal->dcr_host, 0x100);
726 kfree(mal);
733 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev);
735 MAL_DBG(mal, "remove" NL);
738 napi_disable(&mal->napi);
740 if (!list_empty(&mal->list)) {
743 "mal%d: commac list is not empty on remove!\n",
744 mal->index);
750 free_irq(mal->serr_irq, mal);
751 free_irq(mal->txde_irq, mal);
752 free_irq(mal->txeob_irq, mal);
753 free_irq(mal->rxde_irq, mal);
754 free_irq(mal->rxeob_irq, mal);
756 mal_reset(mal);
758 mal_dbg_unregister(mal);
762 (NUM_TX_BUFF * mal->num_tx_chans +
763 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
764 mal->bd_dma);
765 kfree(mal);