Lines Matching refs:write_rreg
51 static void write_rreg(u_long base, u_int reg, u_int val)
212 write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP);
221 write_rreg (dev->base_addr, i, 0);
224 write_rreg (dev->base_addr, i, p[0] | (p[1] << 8));
230 write_rreg (dev->base_addr, MODE, i);
231 write_rreg (dev->base_addr, POLLINT, 0);
232 write_rreg (dev->base_addr, SIZERXR, -RX_BUFFERS);
233 write_rreg (dev->base_addr, SIZETXR, -TX_BUFFERS);
264 write_rreg (dev->base_addr, BASERXL, priv->rxhdr);
265 write_rreg (dev->base_addr, BASERXH, 0);
266 write_rreg (dev->base_addr, BASETXL, priv->txhdr);
267 write_rreg (dev->base_addr, BASERXH, 0);
268 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
269 write_rreg (dev->base_addr, CSR3, CSR3_IDONM|CSR3_BABLM|CSR3_DXSUFLO);
270 write_rreg (dev->base_addr, CSR4, CSR4_APAD_XMIT|CSR4_MFCOM|CSR4_RCVCCOM|CSR4_TXSTRTM|CSR4_JABM);
271 write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT);
336 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
337 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
402 write_rreg(dev->base_addr, CTRL1, CTRL1_SPND);
418 write_rreg(dev->base_addr, i + LADRL, multi_hash[i]);
423 write_rreg(dev->base_addr, MODE, mode);
429 write_rreg(dev->base_addr, CTRL1, 0);
471 write_rreg (dev->base_addr, CSR0, CSR0_TDMD|CSR0_IENA);
605 write_rreg(dev->base_addr, CSR0, status &
650 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
651 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);