Lines Matching refs:tmio
30 #include <linux/mfd/tmio.h>
133 struct tmio_nand *tmio = mtd_to_tmio(mtd);
155 tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
156 tmio->read_good = 0;
165 struct tmio_nand *tmio = mtd_to_tmio(mtd);
167 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
172 struct tmio_nand *tmio = __tmio;
173 struct nand_chip *nand_chip = &tmio->chip;
176 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
179 dev_warn(&tmio->dev->dev, "spurious interrupt\n");
194 struct tmio_nand *tmio = mtd_to_tmio(mtd);
198 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
199 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
206 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
207 dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n",
212 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
213 dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
226 *tmio->read_good.
230 struct tmio_nand *tmio = mtd_to_tmio(mtd);
233 if (tmio->read_good--)
234 return tmio->read;
236 data = tmio_ioread16(tmio->fcr + FCR_DATA);
237 tmio->read = data >> 8;
250 struct tmio_nand *tmio = mtd_to_tmio(mtd);
252 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
257 struct tmio_nand *tmio = mtd_to_tmio(mtd);
259 tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
265 struct tmio_nand *tmio = mtd_to_tmio(mtd);
269 if (*(p++) != tmio_ioread16(tmio->fcr + FCR_DATA))
276 struct tmio_nand *tmio = mtd_to_tmio(mtd);
278 tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
279 tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
280 tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
286 struct tmio_nand *tmio = mtd_to_tmio(mtd);
289 tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
291 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
294 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
297 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
301 tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
320 static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
332 tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
335 tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
336 tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
339 tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
343 tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
346 tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
349 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
352 tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
353 tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
354 tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
357 tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
364 static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
368 tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
382 struct tmio_nand *tmio;
394 tmio = kzalloc(sizeof *tmio, GFP_KERNEL);
395 if (!tmio) {
400 tmio->dev = dev;
402 platform_set_drvdata(dev, tmio);
403 mtd = &tmio->mtd;
404 nand_chip = &tmio->chip;
406 mtd->name = "tmio-nand";
408 tmio->ccr = ioremap(ccr->start, resource_size(ccr));
409 if (!tmio->ccr) {
414 tmio->fcr_base = fcr->start & 0xfffff;
415 tmio->fcr = ioremap(fcr->start, resource_size(fcr));
416 if (!tmio->fcr) {
421 retval = tmio_hw_init(dev, tmio);
426 nand_chip->IO_ADDR_R = tmio->fcr;
427 nand_chip->IO_ADDR_W = tmio->fcr;
452 IRQF_DISABLED, dev_name(&dev->dev), tmio);
458 tmio->irq = irq;
488 if (tmio->irq)
489 free_irq(tmio->irq, tmio);
491 tmio_hw_stop(dev, tmio);
493 iounmap(tmio->fcr);
495 iounmap(tmio->ccr);
497 kfree(tmio);
504 struct tmio_nand *tmio = platform_get_drvdata(dev);
506 nand_release(&tmio->mtd);
507 if (tmio->irq)
508 free_irq(tmio->irq, tmio);
509 tmio_hw_stop(dev, tmio);
510 iounmap(tmio->fcr);
511 iounmap(tmio->ccr);
512 kfree(tmio);
545 .driver.name = "tmio-nand",
569 MODULE_ALIAS("platform:tmio-nand");