Lines Matching defs:cafe
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
106 struct cafe_priv *cafe = mtd->priv;
107 int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
108 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
110 cafe_writel(cafe, irqs, NAND_IRQ);
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
113 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
114 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
122 struct cafe_priv *cafe = mtd->priv;
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
129 cafe->datalen += len;
131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
132 len, cafe->datalen);
137 struct cafe_priv *cafe = mtd->priv;
140 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
142 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
144 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
145 len, cafe->datalen);
146 cafe->datalen += len;
151 struct cafe_priv *cafe = mtd->priv;
155 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
163 struct cafe_priv *cafe = mtd->priv;
168 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
173 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
174 ctl1 = cafe->ctl1;
175 cafe->ctl2 &= ~(1<<30);
176 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
177 cafe->ctl1, cafe->nr_data);
181 cafe_writel(cafe, 0, NAND_CTRL2);
192 cafe_writel(cafe, column, NAND_ADDR1);
197 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
200 cafe_writel(cafe, page_addr, NAND_ADDR2);
206 cafe->data_pos = cafe->datalen = 0;
209 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
215 cafe->datalen = 4;
222 cafe->datalen = mtd->writesize + mtd->oobsize - column;
233 cafe->ctl1 = ctl1;
234 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
235 cafe->ctl1, cafe->datalen);
240 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
242 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
245 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
246 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
249 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
250 cafe_writel(cafe, 0x90000000, NAND_IRQ);
252 uint32_t dmactl = 0xc0000000 + cafe->datalen;
261 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
263 cafe->datalen = 0;
269 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
272 cafe_writel(cafe, ctl1, NAND_CTRL1);
282 irqs = cafe_readl(cafe, NAND_IRQ);
287 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
290 cafe_writel(cafe, doneint, NAND_IRQ);
291 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
292 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
295 WARN_ON(cafe->ctl2 & (1<<30));
313 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
317 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
322 struct cafe_priv *cafe = mtd->priv;
324 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
329 cafe->ctl1 |= CTRL1_CHIPSELECT;
331 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
337 struct cafe_priv *cafe = mtd->priv;
338 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
339 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
343 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
385 struct cafe_priv *cafe = mtd->priv;
387 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
388 cafe_readl(cafe, NAND_ECC_RESULT),
389 cafe_readl(cafe, NAND_ECC_SYN01));
394 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
401 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
402 syn[i] = cafe->rs->index_of[tmp & 0xfff];
403 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
406 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
444 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
445 cafe_readl(cafe, NAND_ADDR2) * 2048);
447 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
450 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
523 struct cafe_priv *cafe = mtd->priv;
529 cafe->ctl2 |= (1<<30);
630 struct cafe_priv *cafe;
654 cafe = (void *)(&mtd[1]);
657 mtd->priv = cafe;
660 cafe->pdev = pdev;
661 cafe->mmio = pci_iomap(pdev, 0, 0);
662 if (!cafe->mmio) {
667 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
668 &cafe->dmaaddr, GFP_KERNEL);
669 if (!cafe->dmabuf) {
673 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
675 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
676 if (!cafe->rs) {
681 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
682 cafe->nand.dev_ready = cafe_device_ready;
683 cafe->nand.read_byte = cafe_read_byte;
684 cafe->nand.read_buf = cafe_read_buf;
685 cafe->nand.write_buf = cafe_write_buf;
686 cafe->nand.select_chip = cafe_select_chip;
688 cafe->nand.chip_delay = 0;
691 cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
694 cafe->nand.options |= NAND_SKIP_BBTSCAN;
695 cafe->nand.block_bad = cafe_nand_block_bad;
699 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
703 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
706 timing[0] = cafe_readl(cafe, NAND_TIMING1);
707 timing[1] = cafe_readl(cafe, NAND_TIMING2);
708 timing[2] = cafe_readl(cafe, NAND_TIMING3);
711 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
714 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
720 cafe_writel(cafe, 1, NAND_RESET);
721 cafe_writel(cafe, 0, NAND_RESET);
723 cafe_writel(cafe, timing[0], NAND_TIMING1);
724 cafe_writel(cafe, timing[1], NAND_TIMING2);
725 cafe_writel(cafe, timing[2], NAND_TIMING3);
727 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
736 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
739 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
740 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
741 cafe_writel(cafe, 0, NAND_DMA_CTRL);
743 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
744 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
747 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
748 if (sizeof(cafe->dmaaddr) > 4)
750 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
752 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
754 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
755 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
758 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
759 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
760 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
768 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
770 cafe->ctl2 |= 1<<29; /* 2KiB page size */
774 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
775 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
776 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
778 cafe->nand.ecc.layout = &cafe_oobinfo_512;
779 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
780 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
786 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
787 cafe->nand.ecc.size = mtd->writesize;
788 cafe->nand.ecc.bytes = 14;
789 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
790 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
791 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
792 cafe->nand.write_page = cafe_nand_write_page;
793 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
794 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
795 cafe->nand.ecc.read_page = cafe_nand_read_page;
796 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
813 cafe->parts = parts;
814 dev_info(&cafe->pdev->dev, "%d partitions found\n", nr_parts);
822 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
825 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
827 pci_iounmap(pdev, cafe->mmio);
837 struct cafe_priv *cafe = mtd->priv;
841 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
844 free_rs(cafe->rs);
845 pci_iounmap(pdev, cafe->mmio);
846 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
862 struct cafe_priv *cafe = mtd->priv;
865 cafe_writel(cafe, 1, NAND_RESET);
866 cafe_writel(cafe, 0, NAND_RESET);
867 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
870 cafe_writel(cafe, timing[0], NAND_TIMING1);
871 cafe_writel(cafe, timing[1], NAND_TIMING2);
872 cafe_writel(cafe, timing[2], NAND_TIMING3);
875 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
878 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
879 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
880 cafe_writel(cafe, 0, NAND_DMA_CTRL);
881 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
882 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
885 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
886 if (sizeof(cafe->dmaaddr) > 4)
888 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
890 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
893 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);