Lines Matching refs:saa7146_write
68 saa7146_write(budget->dev, MC1, MASK_20); // DMA3 off
82 saa7146_write(dev, MC1, MASK_20); // DMA3 off
86 saa7146_write(dev, PCI_BT_V1, 0x001c0000 | (saa7146_read(dev, PCI_BT_V1) & ~0x001f0000));
102 saa7146_write(dev, DD1_INIT, 0x04000000);
103 saa7146_write(dev, MC2, (MASK_09 | MASK_25));
104 saa7146_write(dev, BRS_CTRL, 0x00000000);
107 saa7146_write(dev, DD1_INIT, 0x00000200);
108 saa7146_write(dev, MC2, (MASK_10 | MASK_26));
109 saa7146_write(dev, BRS_CTRL, 0x60000000);
115 saa7146_write(dev, DD1_INIT, 0x06000200);
116 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
117 saa7146_write(dev, BRS_CTRL, 0x00000000);
119 saa7146_write(dev, DD1_INIT, 0x00000600);
120 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
121 saa7146_write(dev, BRS_CTRL, 0x60000000);
126 saa7146_write(dev, DD1_INIT, 0x06000200);
127 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
128 saa7146_write(dev, BRS_CTRL, 0x00000000);
130 saa7146_write(dev, DD1_INIT, 0x02000600);
131 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
132 saa7146_write(dev, BRS_CTRL, 0x60000000);
136 saa7146_write(dev, MC2, (MASK_08 | MASK_24));
139 saa7146_write(dev, BASE_ODD3, 0);
142 saa7146_write(dev, BASE_EVEN3, budget->buffer_height * budget->buffer_width);
145 saa7146_write(dev, BASE_EVEN3, 0);
147 saa7146_write(dev, PROT_ADDR3, budget->buffer_size);
148 saa7146_write(dev, BASE_PAGE3, budget->pt.dma | ME1 | 0x90);
150 saa7146_write(dev, PITCH3, budget->buffer_width);
151 saa7146_write(dev, NUM_LINE_BYTE3,
154 saa7146_write(dev, MC2, (MASK_04 | MASK_20));
158 saa7146_write(dev, MC1, (MASK_04 | MASK_20)); /* DMA3 on */
252 saa7146_write(saa, DEBI_COMMAND, (count << 17) | 0x10000 | (addr & 0xffff));
253 saa7146_write(saa, DEBI_CONFIG, config);
254 saa7146_write(saa, DEBI_PAGE, 0);
255 saa7146_write(saa, MC2, (2 << 16) | 2);
291 saa7146_write(saa, DEBI_COMMAND, (count << 17) | 0x00000 | (addr & 0xffff));
292 saa7146_write(saa, DEBI_CONFIG, config);
293 saa7146_write(saa, DEBI_PAGE, 0);
294 saa7146_write(saa, DEBI_AD, value);
295 saa7146_write(saa, MC2, (2 << 16) | 2);
480 saa7146_write(dev, DD1_STREAM_B, 0x00000000);
481 saa7146_write(dev, MC2, (MASK_09 | MASK_25));
482 saa7146_write(dev, MC2, (MASK_10 | MASK_26));
483 saa7146_write(dev, DD1_INIT, 0x02000000);
484 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
496 saa7146_write(dev, GPIO_CTRL, 0x500000); /* GPIO 3 = 1 */
518 saa7146_write(dev, PCI_BT_V1, 0x001c0000);
520 saa7146_write(dev, GPIO_CTRL, 0x000000);