Lines Matching refs:state
61 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
75 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
80 { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
81 { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 },
82 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
86 b[1] = state->shadow[(reg - 1) & 0xff];
88 if (state->config->repeated_start_workaround) {
89 ret = i2c_transfer(state->i2c, msg, 3);
93 ret = i2c_transfer(state->i2c, &msg[1], 1);
96 ret = i2c_transfer(state->i2c, &msg[2], 1);
101 /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
106 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
109 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
112 /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
113 err = i2c_transfer(state->i2c, &msg, 1);
118 state->shadow[reg] = data;
125 struct s5h1420_state* state = fe->demodulator_priv;
131 s5h1420_writereg(state, 0x3c,
132 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
136 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
140 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
150 struct s5h1420_state* state = fe->demodulator_priv;
155 s5h1420_writereg(state, 0x3b,
156 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
160 s5h1420_writereg(state, 0x3b,
161 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
172 struct s5h1420_state* state = fe->demodulator_priv;
183 val = s5h1420_readreg(state, 0x3b);
184 s5h1420_writereg(state, 0x3b, 0x02);
189 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
193 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
199 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
208 s5h1420_writereg(state, 0x3b, val);
217 struct s5h1420_state* state = fe->demodulator_priv;
225 val = s5h1420_readreg(state, 0x3b);
226 s5h1420_writereg(state, 0x3b, 0x82);
232 if (!(s5h1420_readreg(state, 0x3b) & 0x80))
242 if (s5h1420_readreg(state, 0x49)) {
248 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
257 reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
262 s5h1420_writereg(state, 0x3b, val);
269 struct s5h1420_state* state = fe->demodulator_priv;
275 val = s5h1420_readreg(state, 0x3b);
276 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
280 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
285 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
290 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
299 s5h1420_writereg(state, 0x3b, val);
304 static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state)
309 val = s5h1420_readreg(state, 0x14);
314 val = s5h1420_readreg(state, 0x36);
327 struct s5h1420_state* state = fe->demodulator_priv;
335 /* determine lock state */
336 *status = s5h1420_get_status_bits(state);
341 val = s5h1420_readreg(state, Vit10);
344 s5h1420_writereg(state, Vit09, 0x13);
346 s5h1420_writereg(state, Vit09, 0x1b);
350 *status = s5h1420_get_status_bits(state);
355 if ((*status & FE_HAS_LOCK) && !state->postlocked) {
358 u32 tmp = s5h1420_getsymbolrate(state);
359 switch (s5h1420_readreg(state, Vit10) & 0x07) {
372 tmp = state->fclk / tmp;
394 s5h1420_writereg(state, FEC01, 0x18);
395 s5h1420_writereg(state, FEC01, 0x10);
396 s5h1420_writereg(state, FEC01, val);
399 val = s5h1420_readreg(state, Mpeg02);
400 s5h1420_writereg(state, Mpeg02, val | (1 << 6));
403 val = s5h1420_readreg(state, QPSK01) & 0x7f;
404 s5h1420_writereg(state, QPSK01, val);
408 if (s5h1420_getsymbolrate(state) >= 20000000) {
409 s5h1420_writereg(state, Loop04, 0x8a);
410 s5h1420_writereg(state, Loop05, 0x6a);
412 s5h1420_writereg(state, Loop04, 0x58);
413 s5h1420_writereg(state, Loop05, 0x27);
417 state->postlocked = 1;
427 struct s5h1420_state* state = fe->demodulator_priv;
429 s5h1420_writereg(state, 0x46, 0x1d);
432 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
439 struct s5h1420_state* state = fe->demodulator_priv;
441 u8 val = s5h1420_readreg(state, 0x15);
450 struct s5h1420_state* state = fe->demodulator_priv;
452 s5h1420_writereg(state, 0x46, 0x1f);
455 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
460 static void s5h1420_reset(struct s5h1420_state* state)
463 s5h1420_writereg (state, 0x01, 0x08);
464 s5h1420_writereg (state, 0x01, 0x00);
468 static void s5h1420_setsymbolrate(struct s5h1420_state* state,
479 do_div(val, (state->fclk / 1000));
483 v = s5h1420_readreg(state, Loop01);
484 s5h1420_writereg(state, Loop01, v & 0x7f);
485 s5h1420_writereg(state, Tnco01, val >> 16);
486 s5h1420_writereg(state, Tnco02, val >> 8);
487 s5h1420_writereg(state, Tnco03, val & 0xff);
488 s5h1420_writereg(state, Loop01, v | 0x80);
492 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
494 return state->symbol_rate;
497 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
506 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
510 v = s5h1420_readreg(state, Loop01);
511 s5h1420_writereg(state, Loop01, v & 0xbf);
512 s5h1420_writereg(state, Pnco01, val >> 16);
513 s5h1420_writereg(state, Pnco02, val >> 8);
514 s5h1420_writereg(state, Pnco03, val & 0xff);
515 s5h1420_writereg(state, Loop01, v | 0x40);
519 static int s5h1420_getfreqoffset(struct s5h1420_state* state)
523 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
524 val = s5h1420_readreg(state, 0x0e) << 16;
525 val |= s5h1420_readreg(state, 0x0f) << 8;
526 val |= s5h1420_readreg(state, 0x10);
527 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
534 val = (((-val) * (state->fclk/1000000)) / (1<<24));
539 static void s5h1420_setfec_inversion(struct s5h1420_state* state,
548 inversion = state->config->invert ? 0x08 : 0;
550 inversion = state->config->invert ? 0 : 0x08;
587 s5h1420_writereg(state, Vit08, vit08);
588 s5h1420_writereg(state, Vit09, vit09);
592 static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
594 switch(s5h1420_readreg(state, 0x32) & 0x07) {
617 static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
619 if (s5h1420_readreg(state, 0x32) & 0x08)
628 struct s5h1420_state* state = fe->demodulator_priv;
638 frequency_delta = p->frequency - state->tunedfreq;
642 (state->fec_inner == p->u.qpsk.fec_inner) &&
643 (state->symbol_rate == p->u.qpsk.symbol_rate)) {
653 s5h1420_setfreqoffset(state, p->frequency - tmp);
655 s5h1420_setfreqoffset(state, 0);
663 s5h1420_reset(state);
667 state->fclk = 80000000;
669 state->fclk = 59000000;
671 state->fclk = 86000000;
673 state->fclk = 88000000;
675 state->fclk = 44000000;
678 switch (state->fclk) {
696 dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
697 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
698 s5h1420_writereg(state, PLL02, 0x40);
699 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
703 s5h1420_writereg(state, QPSK01, 0xae | 0x10);
705 s5h1420_writereg(state, QPSK01, 0xac | 0x10);
708 s5h1420_writereg(state, CON_1, 0x00);
709 s5h1420_writereg(state, QPSK02, 0x00);
710 s5h1420_writereg(state, Pre01, 0xb0);
712 s5h1420_writereg(state, Loop01, 0xF0);
713 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
714 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
716 s5h1420_writereg(state, Loop04, 0x79);
718 s5h1420_writereg(state, Loop04, 0x58);
719 s5h1420_writereg(state, Loop05, 0x6b);
722 s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
724 s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
726 s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
728 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
730 s5h1420_writereg(state, Sync01, 0x33);
731 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
732 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
733 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
735 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
736 s5h1420_writereg(state, DiS03, 0x00);
737 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
744 s5h1420_setfreqoffset(state, 0);
748 s5h1420_setsymbolrate(state, p);
749 s5h1420_setfec_inversion(state, p);
752 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
754 state->fec_inner = p->u.qpsk.fec_inner;
755 state->symbol_rate = p->u.qpsk.symbol_rate;
756 state->postlocked = 0;
757 state->tunedfreq = p->frequency;
766 struct s5h1420_state* state = fe->demodulator_priv;
768 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
769 p->inversion = s5h1420_getinversion(state);
770 p->u.qpsk.symbol_rate = s5h1420_getsymbolrate(state);
771 p->u.qpsk.fec_inner = s5h1420_getfec(state);
810 struct s5h1420_state* state = fe->demodulator_priv;
813 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
815 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
820 struct s5h1420_state* state = fe->demodulator_priv;
823 state->CON_1_val = state->config->serial_mpeg << 4;
824 s5h1420_writereg(state, 0x02, state->CON_1_val);
826 s5h1420_reset(state);
833 struct s5h1420_state* state = fe->demodulator_priv;
834 state->CON_1_val = 0x12;
835 return s5h1420_writereg(state, 0x02, state->CON_1_val);
840 struct s5h1420_state* state = fe->demodulator_priv;
841 i2c_del_adapter(&state->tuner_i2c_adapter);
842 kfree(state);
852 struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
854 u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
858 m[0].addr = state->config->demod_address;
864 return i2c_transfer(state->i2c, m, 1+num) == 1 + num ? num : -EIO;
874 struct s5h1420_state *state = fe->demodulator_priv;
875 return &state->tuner_i2c_adapter;
884 /* allocate memory for the internal state */
885 struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
888 if (state == NULL)
891 /* setup the state */
892 state->config = config;
893 state->i2c = i2c;
894 state->postlocked = 0;
895 state->fclk = 88000000;
896 state->tunedfreq = 0;
897 state->fec_inner = FEC_NONE;
898 state->symbol_rate = 0;
901 i = s5h1420_readreg(state, ID01);
905 memset(state->shadow, 0xff, sizeof(state->shadow));
908 state->shadow[i] = s5h1420_readreg(state, i);
911 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
912 state->frontend.demodulator_priv = state;
915 strlcpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
916 sizeof(state->tuner_i2c_adapter.name));
917 state->tuner_i2c_adapter.class = I2C_CLASS_TV_DIGITAL,
918 state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
919 state->tuner_i2c_adapter.algo_data = NULL;
920 i2c_set_adapdata(&state->tuner_i2c_adapter, state);
921 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
926 return &state->frontend;
929 kfree(state);