Lines Matching refs:sclk
160 u32 sclk, mclk;
168 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].sclk;
170 if (sclk > rdev->clock.default_sclk)
171 sclk = rdev->clock.default_sclk;
179 if (sclk < rdev->pm.current_sclk)
196 if (sclk != rdev->pm.current_sclk) {
198 radeon_set_engine_clock(rdev, sclk);
200 rdev->pm.current_sclk = sclk;
201 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
319 clock_info->sclk * 10,
324 clock_info->sclk * 10,