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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/nouveau/

Lines Matching defs:evo

68 	struct nouveau_channel *evo = dev_priv->evo;
77 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
82 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
84 OUT_RING(evo, 0);
86 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
90 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
91 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
98 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
103 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
104 OUT_RING(evo, nv_crtc->lut.depth == 8 ?
107 OUT_RING(evo, (nv_crtc->lut.nvbo->bo.mem.mm_node->start <<
110 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
111 OUT_RING(evo, NvEvoVRAM);
114 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
115 OUT_RING(evo, nv_crtc->fb.offset >> 8);
116 OUT_RING(evo, 0);
117 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
120 OUT_RING(evo, NvEvoFB32);
123 OUT_RING(evo, NvEvoFB16);
125 OUT_RING(evo, NvEvoVRAM);
127 OUT_RING(evo, NvEvoVRAM);
139 struct nouveau_channel *evo = dev_priv->evo;
144 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
150 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1);
152 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON);
154 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF);
157 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
158 OUT_RING(evo, 0);
159 FIRE_RING(evo);
190 struct nouveau_channel *evo = dev_priv->evo;
236 ret = RING_SPACE(evo, update ? 7 : 5);
242 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
246 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_ACTIVE);
248 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_INACTIVE);
251 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
252 OUT_RING(evo, outY << 16 | outX);
253 OUT_RING(evo, outY << 16 | outX);
256 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
257 OUT_RING(evo, 0);
258 FIRE_RING(evo);
468 struct nouveau_channel *evo = dev_priv->evo;
476 ret = RING_SPACE(evo, 2);
481 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
482 OUT_RING (evo, 0);
483 FIRE_RING (evo);
500 struct nouveau_channel *evo = dev_priv->evo;
542 ret = RING_SPACE(evo, 2);
546 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
548 OUT_RING(evo, NvEvoFB32);
551 OUT_RING(evo, NvEvoFB16);
553 OUT_RING(evo, NvEvoVRAM);
556 ret = RING_SPACE(evo, 12);
560 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
561 OUT_RING(evo, nv_crtc->fb.offset >> 8);
562 OUT_RING(evo, 0);
563 OUT_RING(evo, (drm_fb->height << 16) | drm_fb->width);
565 OUT_RING(evo, drm_fb->pitch | (1 << 20));
567 OUT_RING(evo, ((drm_fb->pitch / 4) << 4) |
571 OUT_RING(evo, (fb->nvbo->tile_flags << 8) | format);
573 OUT_RING(evo, format);
575 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
576 OUT_RING(evo, fb->base.depth == 8 ?
579 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
580 OUT_RING(evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
581 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
582 OUT_RING(evo, (y << 16) | x);
590 ret = RING_SPACE(evo, 2);
593 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
594 OUT_RING(evo, 0);
595 FIRE_RING(evo);
608 struct nouveau_channel *evo = dev_priv->evo;
652 ret = RING_SPACE(evo, 17);
656 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
657 OUT_RING(evo, adjusted_mode->clock | 0x800000);
658 OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
660 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
661 OUT_RING(evo, 0);
662 OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
663 OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
664 OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
666 OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
669 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
670 OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
672 OUT_RING(evo, 0);
673 OUT_RING(evo, 0);
676 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
677 OUT_RING(evo, 0);
680 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
681 OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
682 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
683 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));