Lines Matching refs:plane
1066 int plane, i;
1077 dev_priv->cfb_plane = intel_crtc->plane;
1078 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1085 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1101 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1145 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1152 dev_priv->cfb_plane = intel_crtc->plane;
1154 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1171 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1202 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1209 dev_priv->cfb_plane = intel_crtc->plane;
1213 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1231 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1291 * - plane A only (on pre-965)
1314 int plane = intel_crtc->plane;
1369 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1370 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1388 (plane != dev_priv->cfb_plane))
1465 int plane = intel_crtc->plane;
1467 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1468 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1469 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1470 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1471 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1474 switch (plane) {
1479 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1536 if (IS_I965G(dev) || plane == 0)
1556 int plane = intel_crtc->plane;
1565 switch (plane) {
1570 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1864 int plane = intel_crtc->plane;
1867 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1868 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1895 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1960 /* configure and enable CPU plane */
1964 /* Flush the plane changes */
2086 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2089 /* Disable display plane */
2093 /* Flush the plane changes */
2098 if (dev_priv->cfb_plane == plane &&
2264 int plane = intel_crtc->plane;
2266 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2267 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2297 /* Enable the plane */
2301 /* Flush the plane changes */
2307 if ((IS_I965G(dev) || plane == 0))
2318 if (dev_priv->cfb_plane == plane &&
2322 /* Disable display plane */
2326 /* Flush the plane changes */
2362 * Sets the power management mode of the pipe and plane.
2738 * Calculate the watermark level (the level at which the display plane will
2877 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2884 if (plane)
2888 plane ? "B" : "A", size);
2893 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2900 if (plane)
2905 plane ? "B" : "A", size);
2910 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2920 plane ? "B" : "A",
2926 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2936 plane ? "B" : "A", size);
3045 /* Calc sr entries for one plane configs */
3066 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3101 /* Calc sr entries for one plane configs */
3129 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3177 /* Update per-plane FIFO sizes */
3192 /* Calc sr entries for one plane configs */
3276 /* Need htotal for all active display plane */
3280 if (intel_crtc->plane == 0)
3287 /* Calculate and update the watermark for plane A */
3318 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3321 /* Calculate and update the watermark for plane B */
3352 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3358 * display plane is used.
3372 /* calculate the self-refresh watermark for display plane */
3394 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3406 * and plane configuration.
3425 * surface width = hdisplay for normal plane and 64 for cursor
3451 if (intel_crtc->plane == 0) {
3452 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3456 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3487 int plane = intel_crtc->plane;
3491 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3499 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3500 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3838 /* Set up the display plane register */
3841 /* Ironlake's plane is forced to pipe, bit 24 is to
4085 /* Flush the plane changes */
4908 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4919 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4922 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4927 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4931 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5010 if (intel_crtc->plane)
5030 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5038 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5051 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5062 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5075 trace_i915_flip_request(intel_crtc->plane, obj);
5129 intel_crtc->plane = pipe;
5138 intel_crtc->plane = pipe;
5141 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5145 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5146 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5935 /* Disable the VGA plane that we never use */