Lines Matching refs:BIT0
421 #define RXRDYE BIT0
433 #define BRKE BIT0
434 #define IDLD BIT0
2180 while((status = read_reg(info,CST0)) & BIT0)
2365 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2382 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2418 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2596 if (status & BIT0 << shift)
2605 if (dmastatus & BIT0 << shift)
4038 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4041 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4056 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4426 RegValue |= BIT0;
4439 RegValue |= (BIT1 + BIT0);
4464 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4636 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4638 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4762 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4777 RegValue &= ~BIT0;
4779 RegValue |= BIT0;