Lines Matching refs:TxControl
359 Byte_t TxControl[4];
383 (ChP)->TxControl[3] &= ~SETBREAK; \
384 out32((ChP)->IndexAddr,(ChP)->TxControl); \
395 (ChP)->TxControl[3] &= ~SET_DTR; \
396 out32((ChP)->IndexAddr,(ChP)->TxControl); \
408 (ChP)->TxControl[3] &= ~SET_RTS; \
409 out32((ChP)->IndexAddr,(ChP)->TxControl); \
482 (ChP)->TxControl[2] &= ~CTSFC_EN; \
483 out32((ChP)->IndexAddr,(ChP)->TxControl); \
508 (ChP)->TxControl[2] &= ~PARITY_EN; \
509 out32((ChP)->IndexAddr,(ChP)->TxControl); \
520 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
521 out32((ChP)->IndexAddr,(ChP)->TxControl); \
560 (ChP)->TxControl[3] &= ~TX_ENABLE; \
561 out32((ChP)->IndexAddr,(ChP)->TxControl); \
597 (ChP)->TxControl[2] |= CTSFC_EN; \
598 out32((ChP)->IndexAddr,(ChP)->TxControl); \
626 (ChP)->TxControl[2] |= PARITY_EN; \
627 out32((ChP)->IndexAddr,(ChP)->TxControl); \
642 (ChP)->TxControl[2] |= RTSTOG_EN; \
643 (ChP)->TxControl[3] &= ~SET_RTS; \
644 out32((ChP)->IndexAddr,(ChP)->TxControl); \
701 (ChP)->TxControl[3] |= TX_ENABLE; \
702 out32((ChP)->IndexAddr,(ChP)->TxControl); \
913 (ChP)->TxControl[3] |= SETBREAK; \
914 out32((ChP)->IndexAddr,(ChP)->TxControl); \
939 (ChP)->TxControl[2] &= ~DATA8BIT; \
940 out32((ChP)->IndexAddr,(ChP)->TxControl); \
951 (ChP)->TxControl[2] |= DATA8BIT; \
952 out32((ChP)->IndexAddr,(ChP)->TxControl); \
963 (ChP)->TxControl[3] |= SET_DTR; \
964 out32((ChP)->IndexAddr,(ChP)->TxControl); \
980 (ChP)->TxControl[2] |= EVEN_PAR; \
981 out32((ChP)->IndexAddr,(ChP)->TxControl); \
997 (ChP)->TxControl[2] &= ~EVEN_PAR; \
998 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1010 (ChP)->TxControl[3] |= SET_RTS; \
1011 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1048 (ChP)->TxControl[2] &= ~STOP2; \
1049 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1060 (ChP)->TxControl[2] |= STOP2; \
1061 out32((ChP)->IndexAddr,(ChP)->TxControl); \