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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/ata/

Lines Matching defs:hcr_base

255 	void __iomem *hcr_base;
262 void __iomem *hcr_base)
277 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
390 void __iomem *hcr_base = host_priv->hcr_base;
391 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
436 void __iomem *hcr_base = host_priv->hcr_base;
437 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
440 ioread32(CQ + hcr_base),
441 ioread32(CA + hcr_base),
442 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
444 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
447 iowrite32(1 << tag, CQ + hcr_base);
450 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
453 ioread32(CE + hcr_base),
454 ioread32(DE + hcr_base),
455 ioread32(CC + hcr_base),
465 void __iomem *hcr_base = host_priv->hcr_base;
466 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
526 void __iomem *hcr_base = host_priv->hcr_base;
530 ioread32(CQ + hcr_base),
531 ioread32(CA + hcr_base),
532 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
537 temp = ioread32(hcr_base + HCONTROL);
538 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
541 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
547 void __iomem *hcr_base = host_priv->hcr_base;
551 temp = ioread32(hcr_base + HSTATUS);
556 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
559 temp = ioread32(hcr_base + HCONTROL);
560 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
563 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
569 void __iomem *hcr_base = host_priv->hcr_base;
572 temp = ioread32(hcr_base + HCONTROL);
573 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
579 void __iomem *hcr_base = host_priv->hcr_base;
582 temp = ioread32(hcr_base + HCONTROL);
584 iowrite32(temp, hcr_base + HCONTROL);
587 temp = ioread32(hcr_base + HCONTROL);
588 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
599 void __iomem *hcr_base = host_priv->hcr_base;
629 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
639 temp = ioread32(hcr_base + HCONTROL);
640 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
642 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
643 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
644 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
665 void __iomem *hcr_base = host_priv->hcr_base;
671 temp = ioread32(hcr_base + HCONTROL);
674 iowrite32(temp, hcr_base + HCONTROL);
677 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
689 void __iomem *hcr_base = host_priv->hcr_base;
693 temp = ioread32(hcr_base + SIGNATURE);
696 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
697 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
712 void __iomem *hcr_base = host_priv->hcr_base;
723 temp = ioread32(hcr_base + HCONTROL);
725 iowrite32(temp, hcr_base + HCONTROL);
728 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
745 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
746 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
760 temp = ioread32(hcr_base + HCONTROL);
763 iowrite32(temp, hcr_base + HCONTROL);
765 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
774 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
775 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
783 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
787 ioread32(hcr_base + HSTATUS));
796 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
827 void __iomem *hcr_base = host_priv->hcr_base;
871 ioread32(CQ + hcr_base),
872 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
874 iowrite32(0xFFFF, CC + hcr_base);
876 iowrite32(pmp, CQPMP + hcr_base);
877 iowrite32(1, CQ + hcr_base);
879 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
884 ioread32(CQ + hcr_base),
885 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
889 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
890 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
912 iowrite32(pmp, CQPMP + hcr_base);
913 iowrite32(1, CQ + hcr_base);
921 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
939 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
940 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
971 void __iomem *hcr_base = host_priv->hcr_base;
979 hstatus = ioread32(hcr_base + HSTATUS);
980 cereg = ioread32(hcr_base + CE);
996 hstatus, cereg, ioread32(hcr_base + DE), SError);
1034 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1038 dereg = ioread32(hcr_base + DE);
1039 iowrite32(dereg, hcr_base + DE);
1040 iowrite32(cereg, hcr_base + CE);
1059 dereg = ioread32(hcr_base + DE);
1060 iowrite32(dereg, hcr_base + DE);
1061 iowrite32(cereg, hcr_base + CE);
1094 void __iomem *hcr_base = host_priv->hcr_base;
1099 hstatus = ioread32(hcr_base + HSTATUS);
1115 done_mask = ioread32(hcr_base + CC);
1120 ioread32(hcr_base + CA),
1121 ioread32(hcr_base + CE),
1122 ioread32(hcr_base + CQ),
1128 iowrite32(done_mask, hcr_base + CC);
1132 done_mask, ioread32(hcr_base + CA),
1133 ioread32(hcr_base + CE));
1143 i, ioread32(hcr_base + CC),
1144 ioread32(hcr_base + CA));
1150 iowrite32(1, hcr_base + CC);
1154 ioread32(hcr_base + CC));
1162 ioread32(hcr_base + CC));
1163 iowrite32(done_mask, hcr_base + CC);
1172 void __iomem *hcr_base = host_priv->hcr_base;
1178 interrupt_enables = ioread32(hcr_base + HSTATUS);
1198 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1213 void __iomem *hcr_base = host_priv->hcr_base;
1223 temp = ioread32(hcr_base + HSTATUS);
1225 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1228 temp = ioread32(hcr_base + HCONTROL);
1229 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1232 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1233 iowrite32(0x01000000, hcr_base + ICC);
1236 iowrite32(0x00000FFFF, hcr_base + CE);
1237 iowrite32(0x00000FFFF, hcr_base + DE);
1244 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1245 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1299 void __iomem *hcr_base = NULL;
1312 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1313 if (!hcr_base)
1316 ssr_base = hcr_base + 0x100;
1317 csr_base = hcr_base + 0x140;
1327 host_priv->hcr_base = hcr_base;
1361 if (hcr_base)
1362 iounmap(hcr_base);
1379 iounmap(host_priv->hcr_base);
1397 void __iomem *hcr_base = host_priv->hcr_base;
1409 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);