Lines Matching defs:via2
39 volatile __u8 *via1, *via2;
108 via2 = NULL;
112 via2 = (void *) RBV_BASE;
135 via2 = (void *) VIA2_BASE;
150 printk(KERN_INFO "VIA2 at %p is ", via2);
236 via2[gIER] = 0x7F;
237 via2[gIFR] = 0x7F | rbv_clear;
239 via2[vT1LL] = 0;
240 via2[vT1LH] = 0;
241 via2[vT1CL] = 0;
242 via2[vT1CH] = 0;
243 via2[vT2CL] = 0;
244 via2[vT2CH] = 0;
245 via2[vACR] &= ~0xC0; /* setup T1 timer with no PB7 output */
246 via2[vACR] &= ~0x03; /* disable port A & B latches */
259 via2[vPCR] = 0x66;
263 via2[vPCR] = 0x22;
306 "via2", (void *) via2))
307 pr_err("Couldn't register %s interrupt\n", "via2");
309 IRQ_FLG_LOCK|IRQ_FLG_FAST, "nubus", (void *) via2))
327 (uint) via2[rIFR], (uint) via2[rIER]);
329 (uint) via2[rSIFR], (uint) via2[rSIER]);
332 (uint) via2[vDirA], (uint) via2[vDirB],
333 (uint) via2[vACR]);
335 (uint) via2[vPCR],
336 (uint) via2[vIFR], (uint) via2[vIER]);
370 via2[gBufB] &= ~VIA2B_vMode32;
371 via2[gBufB] |= VIA2B_vMode32;
381 if (!via2) {
386 return (int) via2[gBufB] & VIA2B_vCDis;
401 via2[vDirB] |= 0x02;
405 via2[gBufB] |= 0x02;
419 via2[vDirA] &= 0xC0;
422 via2[vDirA] &= 0x80;
427 via2[rSIER] = 0x7F;
433 via2[vBufA] |= 0x7F;
434 via2[vDirA] |= 0x7F;
472 events = via2[gIFR] & via2[gIER] & 0x7F;
480 via2[gIFR] = irq_bit | rbv_clear;
499 events = ~via2[gBufA] & 0x7F;
501 events &= via2[rSIER];
503 events &= ~via2[vDirA];
520 via2[gIFR] = 0x02 | rbv_clear;
521 events = ~via2[gBufA] & 0x7F;
523 events &= via2[rSIER];
525 events &= ~via2[vDirA];
542 via2[gIER] = IER_SET_BIT(irq_idx);
549 via2[gIER] = IER_SET_BIT(1);
555 via2[rSIER] = IER_SET_BIT(irq_idx);
563 via2[vDirA] &= ~(1 << irq_idx);
580 via2[gIER] = IER_CLR_BIT(irq_idx);
586 via2[gIER] = IER_CLR_BIT(1);
589 via2[rSIER] = IER_CLR_BIT(irq_idx);
594 via2[vDirA] |= 1 << irq_idx;
608 via2[gIFR] = irq_bit | rbv_clear;
627 return via2[gIFR] & irq_bit;
630 return ~via2[gBufA] & irq_bit;